Satellite decoding set-top box design based on L64724

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Abstract: The internal circuit functions and performance characteristics of L64724 digital video satellite decoding chip produced by LSI are analyzed. The internal structure and pin function of L64724 are given. The implementation scheme of satellite decoder set-top box circuit realized by L64724 is proposed, and the function of the circuit and the configuration method of design parameters are pointed out in combination with the development.
Keywords: satellite decoding set-top box programmable L64724

1 Overview

The development of digital compression technology provides powerful technical support for satellite digital video broadcasting. Although the globally recognized standards have not yet been formed, the proposal of DVB-S in Europe is undoubtedly a reference solution. The L64724 is a more comprehensive digital video satellite decoder chip based on this standard introduced by LSI.

For system designers, the L64724 offers maximum integration and flexibility at the lowest cost, with minimal external components in use.

2 Performance characteristics

The L64724 has the following features:

● Can support DVB and DSS systems;

● BPSK / QPSK rate up to 45 mega-baud;

● There is a square root raised cosine matched filter with a roll-off factor of 20% and 35%;

● With anti-aliasing filter that can work between 1 and 45 megabaud, no need to switch to external SAM or low-pass filter;

● Digital clock synchronization and digital carrier synchronization can be performed on the chip;

● The demodulation mode and tuning control can be automatically obtained by the on-chip microcontroller;

● The integrated phase-locked loop can be used to ensure clock synchronization;

● has a fast channel switching mode;

●Including automatic gain control power supply;

● Contains programmable Viterbi decoding module, including 1/2, 2/3, 3/4, 5/6, 6/7, 7/8 and other speeds, and can achieve automatic synchronization;

● Contains (204/188), (146/130) RS decoder;

● Programmable synchronization of deinterleaving, RS decoding and descrambling;

● Automatic monitoring of channel performance detection;

● The depth of convolution deinterleaving is 12;

● Its serial host interface is compatible with the LSI logic serial control bus interface;

● With buck mode.

3 L64724 internal structure and pin description

3.1 Internal structure

Figure 1 shows the internal functional diagram of the L64724, which mainly consists of two modules: BPSK/QPSK demodulator and FEC decoder. In Fig. 1, the portion above the data and address bus is a BPSK/QPSK demodulator, and the following is an FEC decoder.

The BPSK/QPSK demodulator extracts digital signals from phase-demodulated analog signals.

The FEC decoding module is a complete forward error correction decoder using Viterbi inner code and RS outer code. The decoder contains all possible synchronization, as well as de-interleaving and descrambling.

3.2 Package and pin description

The L64724 is available in 100-pin PQFP and 80-pin TQFP packages. Table 1 lists the commonly used key pin descriptions.

Table 1 Description of the pin of L64724

Pin	Description	Remarks
CLK	RI/Q sampling clock	TTL input
D[7:0]	data input	Double-ended TTL
CS	Chip Select	TTL input
RESET	Chip reset	TTL input
XOIN	External crystal input	CMOS input
READ	Read	TTL pull-up input
CO[7:0]	Channel output	Tri-state output
DBALIDOUT	Data output is valid	CMOS output
ERROROUT	Error indication	Tri-state output
LCLK	Output clock	Output
XOOUT	Output to external crystal	CMOS output
VDD	Digital power supply	enter
VSS	Digitally	enter

4 Application Notes for L64714

The operating parameters of the L64724 are parameters such as DC and AC as well as capacitance. Under normal circumstances, the limit cannot be used for each parameter, otherwise it may cause permanent damage to the chip. The important operating parameters of L64724 are listed in Table 2.

Table 2 Main operating parameters of L64724

Symbol	Parameter Description	The scope of work
VDD	DC supply voltage	-0.3 to +3.9V
VIN	LVTTL input voltage (minutes H and L)	-1.0~VDD+0.3V
IIN	DC input current	10mA
TSTG	Storage temperature range	-40～+125°C
tCYCLE	OCLK and CLK clock cycles	Minimum 11.1ns
Ts	Input to CLK setup time	Minimum TBDns
TH	Input to CLK hold time	Minimum TBDns
TOD	CLK output delay	TBDns
TRWH	High reset pulse width	3 clock cycles
TWK	Wake up time	280 clock cycles

Due to the high parameter requirements of the chip, it is recommended that the user set the DC supply voltage VDD between 3.14 and 3.47V, the operating temperature TA range is 0 to 70 °C, and the chassis temperature Tc is 0 to 85 °C. When TA=25°C, VIN=3.3V, and frequency is 1MHz, it is better to use 5pF scale capacitor as input capacitor CIN and output capacitor COUT.

Table 3 Parameter configuration

Parameter	High rate data	Low rate data
Transmission rate	42.6Mbps (21.3Mbaud)	4.0Mbps (2.0Mbaud)
ADC sampling frequency	50MHz	23.75MHz
Crystal frequency	15MHz	15MHz
ADC analog input	Peak to peak value is 1.0V	Peak to peak value is 1.0V
DC compensation control	No need to	No need to
Viterbi code rate	1/2	1/2
Eb/No	4.0dB	4.0dB
mode	DVB	DVB

5 Typical application of L64724

The use of L64724 must first pay attention to its internal or external interfaces, including channel interface, channel clock interface, channel data output interface, PLL interface, A/D interface, AGC/clock control interface, microcontroller interface, control signal. Interface, etc. The channel interface is used to receive an input signal from a satellite tuning circuit, and the channel clock is used to indicate a data clock, which is triggered by a rising edge. The channel data output interface is the path through which the L64724 sends data. In the implementation circuit of the decoder set top box, the interface should generally be connected to the input of the multiplexer. The microcontroller interface is used to connect the chip to the microcontroller. The control signal interface is used to control the operation of the L64724.

The L64724 is a programmable logic device that we can adapt to different needs by changing its interface and internal register settings. The need for clock and input data is the key to determining circuit stability.

5.1 Data and Clock Control Scheme

As shown in Figure 2, the input clock signal CLK in L64724 can be used to implement a possible configuration in the channel decoding system. It is generated by an external crystal oscillator, and the sampling clock PCLK is generated by CLK through the internal phase-locked loop PLL for driving. Three modules, such as analog-to-digital converter (ADC), demodulator, and forward error correction (FEC). PCLK can work up to about 90MHz. The CLK generated by the crystal oscillator can be used as the reference clock of the PLL, typically between 15 and 60 MHz. The control clock LCLK is obtained by dividing the PLL by CLK-DIV2, that is, LCLK=CLK/CLK-DIV2.

5.2 L64724 application circuit

L64724 is a very comprehensive chip, I deeply appreciate its superior and flexible performance in the application of the circuit. The L64724 is mainly used in satellite digital television receiver implementation circuits, which are designed according to the satellite transmission scheme in the European DVB standard. With this chip, it can achieve a multiplier effect in the design of the receiver box. Figure 3 shows a circuit design for a set-top box design. It consists mainly of three parts. The core part is a satellite decoder consisting of L64724, and the MPEG-2 code stream consisting of L64008 is transmitted to the demultiplexer. The circuit and the video/audio decoder consisting of L64005. When the circuit receives the signal from the satellite, the tuning circuit selects the useful signal and sends it to the L64724. After the signal enters the L64724, the analog signal is sampled into a digital signal by the front end, and the programmable setting is performed inside the L64724. The required parameters, after reaching the specified performance indicators, are then passed to the L64008 demultiplexer for processing via the serial bus. Finally, the data is exchanged with the DRAM and the result is sent to the L64005 for video decoding to become the desired audio and video signals and output in two ways. The serial data bus in FIG. 3 controls each unit in the chip by programming, and the information obtained by each unit in the chip is provided by the bus.

5.3 Parameter configuration in circuit design

In the L64724 application, on-chip parameters can be configured through the microcontroller interface for optimal performance. For the convenience of the reader. Table 3 provides a set of configuration parameters for QPSK demodulation and FEC for high and low data speeds respectively. This configuration is a set of experimentally optimized parameters that can be used by the reader.

6 Conclusion

The satellite decoding receiving circuit can set the parameters of the L64724 in the above circuit, including programming control of the transmission rate, the ADC sampling frequency, the crystal frequency, the code rate of the internal code, and the like. For different parameter configurations, the connection of each pin is also different, and the working conditions of the chip should also be paid attention to avoid permanent damage to the chip. The circuits and parameters described in this paper have been verified by practice, which is a more optimized circuit configuration and the core circuit of the high-definition digital TV receiver in the satellite transmission system.

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