In pulse radar systems, high power amplifiers (HPAs) must be rapidly turned on and off during the transition from transmit to receive. A typical target for conversion time is less than 1 microsecond. Traditionally, this has been achieved using drain control, which involves switching large currents between 28 V and 50 V. While switching power technology can accomplish this, it introduces additional size and circuit complexity. In modern phased array antenna development, where minimizing size, weight, and power (SWaP) is crucial, there's a growing desire to eliminate the complexities of HPA drain switches.
This paper introduces a novel yet simple gate pulse drive circuit that offers an alternative method for fast HPA switching, eliminating the need for drain switch circuitry. The measured switching time is under 200 nanoseconds, providing ample margin over the 1 microsecond target. Additional features include offset programming to address device-to-device variations, gate clamping to protect against voltage spikes, and overshoot compensation to optimize pulse rise time.
A traditional drain pulse configuration involves a series FET that turns on the high voltage supply to the HPA. The control circuit must convert a logic-level signal into a higher voltage to activate the FET. However, this approach presents several challenges, such as managing high current paths with low inductance, ensuring proper discharge of the drain capacitor, and generating voltages above the HPA’s drain voltage when using N-channel FETs. These issues complicate the design and increase SWaP, making it less desirable for modern phased array systems.
To address these challenges, a recommended gate pulse circuit is proposed. This circuit converts a logic-level input into a suitable gate control signal for GaN HPAs, requiring both a negative bias voltage for operation and a larger negative voltage for shutdown. The circuit must also manage gate capacitance, provide a fast rise time, and minimize overshoot.
The proposed circuit uses an operational amplifier in an inverting configuration with a precision DAC to set reference voltages. It includes components for gain adjustment, noise filtering, and gate clamping. The layout is optimized for compactness and performance, making it suitable for high-density phased array applications.
Testing showed that the turn-on time was less than 200 nanoseconds, with a significant margin compared to the 1 microsecond target. The off time was even faster, further confirming the system's capability for rapid transmit-to-receive transitions.
This solution not only improves performance but also reduces system complexity and SWaP, making it ideal for next-generation radar systems. As electronic systems become more integrated, such circuits are expected to play a key role in advancing phased array technologies.
**Author**
Peter Delos is the Technical Lead for the Aerospace and Defense Division at Analog Devices. He holds a BSEE from Virginia Tech University and an MSEE from New Jersey Institute of Technology. With a background in naval nuclear power and extensive experience in radar and electronic warfare systems, he has led the development of advanced phased array systems.
Jarrett Liner is an RF Systems Applications Engineer at Analog Devices, specializing in RF systems and device design. He has worked extensively with GaN amplifiers and RF ICs, and brings valuable hands-on experience from his time in the U.S. Navy. Outside of work, Jarrett enjoys outdoor activities and spending time with his family.
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