Recently, several industry giants including Google, IBM and AMD formed an OpenCAPI open alliance. For the server industry that needs to deal with massive amounts of data, they have jointly launched a brand new open interface framework: "OpenCAPI" (Open Coherent Accelerator Processor Interface, Open Coherent Accelerator Processor Interface.
According to the official website of the OpenCAPI Alliance, there are two major technology trends in the future that will have a profound impact on the entire technology industry. One is the improvement of microprocessor manufacturing process and design level, and the other is the breakthrough of high-performance storage technology. Both of these have promoted the development of areas such as artificial intelligence and machine learning from the bottom, and on the other hand have created a new normal state of the industry that requires massive data processing.
Thus, the OpenCAPI Alliance pointed out that the existing hardware interface standards can no longer meet the development of technology, and its main drawbacks are as follows. One is that the traditional I/O interface standard usually requires a large amount of CPU resources when reading and writing, which greatly reduces the operating efficiency of the entire system. Secondly, most systems nowadays must consider the compatibility of hardware interface specifications put forward by various vendors in the initial design. This is a waste of resources and is not suitable for the future development of the industry.
In this case, the OpenCAPI Alliance pointed out that a completely new open interface standard must be introduced to completely solve the above problems. This is the OpenCAPI interface framework.
According to the OpenCAPI Alliance official website, the OpenCAPI open bus interface framework mainly has the following four advantages.
high performance. The maximum transmission rate of OpenCAPI single channel can reach 25Gbps, while the current more advanced PCI-E 3.0 standard is only 7.877 Gbps, while the former also supports multi-channel binding, which can be doubled at the 25Gbps limit speed. In addition, the OpenCAPI interface can be based on consistent virtual addressing technology to implement peripheral connections in a multi-CPU architecture in the simplest way.
Does not use CPU resources. The OpenCAPI bus allows peripherals to run autonomously in the application space without core involvement, while also enabling collaboration with the host CPU, which greatly improves the overall system's operating efficiency.
Good compatibility. The OpenCAPI bus supports connections for various hardware accelerators, high-performance I/O devices, and high-performance storage devices.
Fully open. The OpenCAPI Bus Alliance is a non-profit organization that is fully open to companies and industry organizations.
Currently, the latest version of the OpenCAPI bus standard is 3.0. IBM said that it will first adapt OpenCAPI in the Power9 server that will be launched in 2017. In addition, AMD also stated that it will introduce OpenCAPI in the Zen architecture server in the future.
In response, industry insiders commented that the introduction of the OpenCAPI interface framework will directly affect the development of the widely used PCI-E interface standard promoted by Intel.
As the successor to the traditional PCI and AGP bus, PCI-E was first proposed by Intel in 2002. Its original name was "3GIO" (ie, 3 Generation I/O). The meaning is obvious. Intel intends to make PCI-E become The specification of the next-generation I/O interface finally achieves the unification of the bus standards.
Compared with traditional standards, the main advantages of the PCI-E interface are speed, flexibility, and compatibility. According to the latest 4.0 specification, the 128-bit/130-bit (128 valid data per 130 bits) encoding method allows PCI-E interface to achieve a maximum single-channel transmission bandwidth of 15.754 Gbps, far exceeding most other buses. standard. In addition, depending on the application scenario, the requirements for cost and bandwidth are also different. The PCI-E specification also provides various line width options such as x1, x4, x8, and x16, providing developers and manufacturers with the largest Convenience, and PCI-E also supports hot swap. Finally, due to the backward compatibility of the PCI interface, all software drivers and system configurations originally implemented for the PCI interface do not need to be re-introduced, and can be used by directly adapting PCI-E directly to the hardware. Reduced the promotion of PCI-E.
It is with these advantages that the PCI-E interface has become a de facto common standard. In addition to being the main board peripheral interface, memory expansion interface, and communication bus under the multi-CPU architecture, PCI-E is also widely used in the solid state. Hard disk and massive data storage and transmission fields.
In the future, the continued development of the OpenCAPI bus interface with higher speed, better performance, and more open posture will inevitably influence Intel's layout in terms of I/O interfaces. What kind of measures Intel will take next, we will wait and see.
Related Reading:
A table tells you how many years Apple's I/O interfaces have lived
If the USB interface stands for 20 years, will wireless technology threaten its status?