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introductionThe audio controller conforming to the Audio Codec'97 protocol (referred to as AC'97, a digital audio processing protocol proposed by Intel Corporation) is widely used not only for personal computer sound cards, but also for SOC of personal information terminal equipment (such as Intel's PXA250). Audio solution. The audio controller designed in this paper provides a digital audio interface to the DSP core. While introducing the structure of the audio controller, the paper emphasizes the coordinated transmission of data between the core and the kernel, and gives a method for functional testing of the audio controller based on FPGA to implement the SoC kernel simulation environment.
The structure and principle of the audio controller
The AC'97 system consists of two parts: the audio codec (Codec) and the audio controller (Controller). The audio codec implements functions such as A/D, D/A conversion, and audio processing, and the audio controller is a digital interface between the SoC core and the audio codec, and is responsible for controlling the serial/parallel of data and audio data. And / string conversion and transmission.
The audio controller of this design complies with AC'97 specification V2.3. Its main indicators are as follows: support for dual-channel recording and playback; support for fixed sampling rate (48kHz) and variable sampling rate recording and playback; 20-bit wide 16-layer deep PCM audio data FIFO; support power saving mode; support interrupt, DMA and polling to achieve data exchange with the kernel or memory.
The main structure of the audio controller that constitutes the structure is shown in Figure 1. The kernel/memory and audio controller interface (CORE/MEMORY, CTRL INTERFACE) connects the audio controller to the kernel or memory. CS is the chip select signal, WR and RD are read and write enable, ADDR (16-bit wide) is the port address of the audio controller, DIN and DOUT (both 32-bit wide) are the input and output data on the bus, IRQ And DMA REQ are interrupts and DMA requests, respectively. The main module (AC'97 CTRL MASTER) is responsible for the PCM audio data, control and status register group (CONTROL&STATUS REGS) data and audio codec between the audio controller (AC'97 CONTROLLER) and the core or memory (in DMA mode). AC'97 CODEC) Internal register data The transmission of each parallel data is synchronized by the main clock CLK. The power control module (POWER CTRL) can initiate the power save mode and is also synchronized by the main clock CLK.
The four sets of FIFOs are used to store PCM audio data, all 20 bits wide and 16 layers deep, so they can support up to 20 bits wide resolution. An interrupt or DMA request can be issued when the FIFO is full or empty. The audio codec internal register read/write buffer (CODEC REG WRITE/READ BUF, referred to as CRBUF) is two 32-bit registers. The write buffer can buffer the control word ready to be written to the internal codec of the audio codec, and can issue an interrupt request when it is empty; the read buffer can buffer the status word that has been read from the internal register of the audio codec, when it is full Issue an interrupt request. The control and status register set contains eight 32-bit registers. The main functions of the general control register are the system cold start and warm start; the general status register reflects the audio codec status; the functions of other registers include configuring the PCM input and output channels, Configure and generate interrupts or DMA requests. The secondary module (AC'97 CTRL SLAVE) implements serial transmission and reception of data frames between the audio controller and the audio codec (AC-LINK). The output data (SDATA_OUT) is synchronized by the rising edge of the secondary clock BIT_CLK, and the input data (SDATA_IN) is synchronized by the falling edge of BIT_CLK.
working principle
The DSP core obtains the audio codec status and sets the audio codec working mode by reading and writing the audio controller CSRS respectively; buffers the PCM audio data during audio recording and playback through the read/write FIFO; and obtains the audio by reading and writing CRBUF Codec internal register status and set audio codec internal register parameters. The following is an example of the main steps in audio playback to introduce the working principle of the audio controller.
(1) Write full PCM left channel output FIFO;
(2) fill the PCM right channel output FIFO;
(3) polling the audio codec to prepare (Codec ready) signal is valid;
(4) Read the 26H register of the audio codec to determine whether the D/A converter is ready;
(5) Allow CRBUF to generate an interrupt request;
(6) Write 0 to the 02H register of the audio codec to make the main tone
(7) Wait for the CRBUF to generate an interrupt, respond to the interrupt and write 0 to the 18H register of the audio codec to minimize the PCM output volume attenuation;
(8) Wait for the CRBUF to generate an interrupt, respond to the interrupt and write 1 to the 2AH register of the audio codec, that is, play the audio at a variable sampling rate;
(9) Wait for CRBUF to generate an interrupt, respond to the interrupt and write 5622 (hexadecimal) to the 2CH register of the audio codec, that is, play the audio at the sampling rate of 22.05 kHz;
(10) Allow the PCM left and right channel FIFO to generate a full interrupt;
(11) Set the PCM left and right channel fixed rate or variable rate transmission, and start playing audio;
(12) Waiting for the PCM code in the FIFO to transfer 16 layers and issue an interrupt request;
(13) determining whether the PCM left channel FIFO issues an interrupt request, and if so, writing 16 layers of PCM left channel data;
(14) determining whether the PCM right channel FIFO issues an interrupt request, and if so, writing 16 layers of PCM right channel FIFO data;
(15) If the PCM data in the memory is read, the playback ends, otherwise return to step 12 to continue playback.
The composition and principle of the SOC simulation environment
It can be seen from the working principle of the audio controller that each step is performed under the control of the DSP core. Therefore, in the function verification of the audio controller, not only to ensure its own logic is correct, but also to ensure that the data transmission with the kernel is correct, thus facilitating the integration of the audio controller and the kernel. It is proposed to approximate the real core through the component SoC kernel simulation environment, and test the designed audio controller in this simulation environment.
The composition of the simulation environment
The hardware of the SoC core emulation environment is based on Xilinx's MICROBlaze multimedia development board, and its core is the Vertex II FPGA. National Semiconductor's AC'97 CODEC LM4549 ​​chip is also integrated on the board, and LINE IN/OUT, headphones and microphone jacks are available. You can test the audio recording and playback effects through these jacks, and you can also debug some key signals through the test points on the board. The composition of the SoC kernel simulation environment is shown in Figure 2.
Figure 2 The composition of the SoC kernel simulation environment
The core analog module (CORE SIM) is the core of the SOC core simulation environment. It is downloaded into the Vertex II FPGA's analog DSP core in a single-cycle instruction in RTL code. It can read and write memory and access the audio controller (including read and write FIFO, CRBUF). And CSRS), respond to and process interrupt requests or DMA requests. Among them, DIN_RAM is a 32-bit memory data input bus; DIN_CTRL is a 32-bit audio controller data input bus; DOUT is a 32-bit data output bus; IRQ is an audio controller interrupt request; DMA REQ is an audio controller DMA request; RST is audio The controller is reset asynchronously.
The block memory module is a single-port memory implemented by block memory in Vertex II FPGAs. This memory has the same timing as conventional SRAM and can simulate up to 126KB of on-chip SRAM. Call CORE Generator in the Xilinx Integrated Development Environment (ISE) to generate
The clock generation module (CLOCK GENERATOR) can issue three clocks of 27MHz, 54MHz and 108MHz, and generates an audio controller asynchronous reset signal RST. The crystal oscillator on the MICROBolaze development board emits a square wave signal of 1:1 duty ratio of 27MHz and 50MHz as the input of the clock generation module. The digital phase-locked loop hard core module (CLOCKGEN.v and CLOCKGEN.ucf) can be used to output multiple times. The frequency clock (108MHz for this design) and the asynchronous reset signal RST. AC'97 CTRL is an audio controller logic that is downloaded to the Vertex II FPGA in RTL form. AC'97 CODEC is National Semiconductor's LM4549 ​​AC'97 CODEC chip.
The implementation principle of the kernel simulation module
The RTL code simulates the instruction execution level in the pipeline, which is the level at which the audio controller and the kernel directly interact with each other. According to the behavior and interface characteristics of the DSP core at the instruction execution level, the interface and internal signals of the kernel analog module can be flexibly changed (by changing the RTL code) to form different simulation environments. Test whether the operation of the audio controller and the core is stable in the new simulation environment. If the result is not satisfactory, the design of the audio controller should be changed. This allows the characteristics of the audio controller to be optimally coordinated with the core.
Playback example based on SoC kernel simulation environment
An example of playing audio based on the SoC core emulation environment is given below. The audio comes from the Utopia Windows Start.wav (153KB, 16-bit mono wave file) in the winnt/media directory after the initial installation of the Windows 2000 operating system. The PCM audio code in the file is extracted and downloaded to the Vertex II block memory. . The audio controller controls the audio codec in the SoC core emulation environment. Connect the headphones to the headphone jack of the MicroBlaze development board. You can hear the audio signal for nearly 3 seconds, which is basically the same as the sound of the original audio file. The audio analysis software Audiocity is used to analyze the audio playback effect. The original audio source is slightly different from the audio played by the development board for the following three reasons. (1) The starting point of the recording of the computer sound card is different from the starting point of the original audio; (2) Since the maximum capacity of the block memory is 126 KB, the recorded waveform file only intercepts the first 2/3 parts of the original file (153 KB). (3) After the sound is played through the SoC core simulation environment, the audio obtained by the computer sound card recording is inevitably different from the original audio. The first and second factors cause the deviation of the two waveforms in the direction of the time axis, and the factor 3 causes the deviation in the direction of the amplitude axis. Despite these differences, it is entirely clear that in the SoC core emulation environment, the designed audio controller logic is functioning correctly and can work in coordination with the kernel.
to sum up
This paper introduces in detail the idea and implementation method of building an SOC kernel simulation environment to test the audio controller according to the structure of the designed audio controller. Based on this simulation environment, not only can the effect and performance of the actual recording and playback of the audio controller be tested, but more importantly, the degree of coordination with the kernel can be reflected in time. This avoids the drawback of designing the audio controller in isolation, regardless of its coordination with the SoC system, and significantly improves the efficiency of the later integrated SoC system.
references
1 Audio Codec '97, Revision 2.3 Revision 1.0, Intel, April 2002
2 MICroBlaze and Multimedia Development Board User Guide UG020 ​​(v1.0), Xilinx, August 2002
3 Core Gennerator Guide - ISE 5, Xilinx
4 LM4549A AC '97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound, National Semiconductor, November 2002
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