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Â− High-resolution image display on analog broadcast and HDTV TVs using the newly developed PXG-4 image quality enhancement technology, eliminating the need for external DRAM or similar chips −
Tokyo, December 20, 2004 - Today Renesas Technology Corporation announces the R2J10030FP PAL/NTSC*1 CRT TV video signal processing LSI, which achieves high image quality in analog TV through digital technology. The image quality enhancement circuit used is only currently One third of Renesas Technology products. In January 2005, sample shipments will begin in Japan.
Since the R2J10030FP uses the newly developed PXG (Pixel Generator Technology)-4 image enhancement technology, the amount of pixel interpolation required for high image quality is reduced. The DRAM or similar external chip used in current large-scale calculations is not required, thereby greatly reducing the size of the image enhancement circuit and achieving the same image quality as digital broadcasting at a low cost.
The characteristics of the R2J10030FP are as follows.
1. High image quality by using PXG-4 image enhancement technology.
PXG-4 is an image enhancement technology developed in collaboration with Niigata Seimitsu Co., Ltd. It can generate interpolated pixels from adjacent horizontal and vertical directions, or diagonally arrange pixels using a function based on Fluency theory*2. Perform pixel interpolation in the horizontal and vertical directions so that the total number of pixels is four times that of the original. With a small-scale circuit, very natural curve reproduction and source signal frequency characteristic enhancement can be realized. For bandwidth-constrained TV broadcasts, DVDs, and similar signals, the overflowing high-band signals can be compensated for by calculations, making this technology very useful for improving image resolution.
In addition, since the vertical direction pixel interpolation processing can generate a new line between horizontal lines, non-interlaced scanning*3 processing can be simultaneously performed.
2. High-definition TV*4 can be manufactured at a very low cost
For compatibility with existing HDTVs, the R2J10030FP supports composite video signals, Y/C, RGB, and digital broadcast formats 576i/480i, 576p/480p, and 1080i (vertical: 50/60 Hz) component signals as input signals. Since the PXG-4 circuit converts the input composite video, Y/C and 576i/480i signals into 576p/480p non-interlaced signals, high-definition images can be obtained by pixel interpolation, eliminating the need for external DRAM, scalar IC, and dual Double-speed scanning deflection ICs, etc. These external components are required for the use of current Renesas technology products for modern television. Therefore, the circuit used is about one-third of the current Renesas technology products, and image enhancement can be realized, and high-definition television can be realized at a very low cost.
3. On-chip 16-bit microcontroller for improved performance and ease of use.
Although the previous 8-bit TV microcontroller is a standard product, the R2J10030FP features a 16-bit on-chip microcontroller and a field-proven Renesas H8S core. Can provide higher processing performance and can be programmed in C language. Also included is the mature OSD*5 feature, which provides multiple text displays.
During the device development process, products with flash memory can be purchased for program debugging.
<Product Background>
Despite the increasing popularity of FPD TVs using LCD or PDP screens in recent years, the demand for CRT TVs is still very large from a global perspective, and it is much cheaper than FPD TVs. At the same time, digital broadcasting is being introduced worldwide, and the demand for high-definition televisions capable of processing digital broadcast high-definition television signals from set-top boxes or similar devices is also rapidly increasing. As a result, demand for high-definition television CRT TVs is growing rapidly in Asia, especially in China, and its demand accounts for about half of the total global TV production. It is expected that demand will continue to grow in the next few years. However, the market price of such TV sets has also been greatly reduced. Therefore, the main concern of every TV manufacturer is how to greatly reduce the cost of high-definition TV sets and obtain reasonable returns.
To meet these needs, Renesas Technology has developed the R2J10030FP PAL/NTSC CRT TV video signal processing chip, which combines proven analog signal processing technology with digital technologies such as the PXG-4 and the built-in microcomputer. 1/3 of Renesas Technology's image enhancement circuit can achieve digital high image quality in analog TV.
<Additional Product Details>
The R2J10030FP includes PAL/NTSC video/color signal processing circuitry, deflection circuitry and a 16-bit microcomputer, and provides all TV baseband processing.
The Fluency theory used by PXG-4 was proposed by Professor Kazuo Toraichi of Tsukuba University. When the pixels are interpolated using the fluency function based on the theory, the influence of the adjacent horizontal, vertical, and diagonally arranged external pixels is considered, and the high-frequency components of the original signal are regenerated by connecting the points with natural curves. Another advantage is that processing can be implemented in small-scale circuits.
By optimizing this interpolation technique, Renesas Technology and Niigata Seimitsu Co., Ltd. have developed "PXG" image enhancement technology for analog TV signals. There are two types of PXG: PXG-2, which only performs horizontal pixel interpolation and doubles the total number of pixels, and PXG-4, which also performs vertical pixel interpolation, so that the total pixels are four times larger. The R2J10030FP uses the PXG-4.
Future plans include the development of a range of CRT TV video signal processing chips, the use of PXG technology and the inclusion of a 16-bit microcomputer, and the development of NTSC products and multi-standard versions supporting PAL, NTSC and SECAM.
Notes: 1. PAL/NTSC: color video system, PAL is used in Europe and China, NTSC is used in Japan and the United States.
2. Fluency Theory: Theory proposed by Professor Kazuo Toraichi of Tsukuba University. Using the fluency function based on the theory to interpolate pixels, taking into account the influence of adjacent horizontal, vertical and diagonally arranged external pixels, by re-generating the high-frequency components of the original signal by connecting the points with natural curves, Thereby improving the high frequency characteristics.
3. Non-interlaced: A sequential scanning method that performs a screen display in a single scan. Compared to the interlaced scanning method commonly used in television, the flicker of the screen can be reduced.
4. High-definition television: A TV that can process digital broadcast high-definition television signals by connecting a set-top box or similar digital broadcast receiver.
5. OSD function: OSD is an abbreviation displayed on the screen, which refers to the function of displaying numbers and characters on the screen.
* Other product names, company names, or trademarks mentioned herein are the property of their respective owners.
<Typical application>
− PAL/NTSC CRT TV
<Japan domestic price> * for reference
| product name | Package | Sample price [tax included] (yen) |
| R2J10030FP | 80-pin LQFP | 3,000 [ 3,150 ] |
<indicator>
| project | index | |
| voltage | 8.7 V, 3.3 V | |
| Supported color system | PAL, NTSC | |
| input signal | Composite, Y/C RGB (synchronized with green), component 50Hz: 576i, 576p, 1080i 60Hz: 480i, 480p, 1080i | |
| Input pin | Compound: 4 systems Y/C: 2 systems (one Y input system shares a pin with a composite system) Compound: 2 systems RGB: 1 system (shared pins with one component system) | |
| Y/C separation (digital comb filter) | PAL: 2-wire, NTSC: 3-wire | |
| thing | Parabola, angle, trapezoid, bow, angle | |
| On-chip microcontroller | CPU core | 16-bit H8S core |
| Memory capacity | ROM: 128 Kbytes, RAM: 4 Kbytes | |
| OSD function | Display characters: 32 characters × 8 line points Configuration: 16 × 20 dot character type: 256 class + 62 class | |
| Package | 80-pin LQFP | |
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