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The H.264/AVC standard has a series of new features superior to MPEG4 and H.263. Under the same reconstructed image quality, H.264 saves about 50% of the code rate over H.263. But the cost of saving the code rate is an increase in algorithm complexity. The real-time decoding process is no longer possible with software alone. So you must use hardware acceleration, which is the original intention of this decoder design.
Although H.264 is half the code rate compared to the H.263 image of the same quality, the target of this decoder is to solve the decoding of H.264 HD image (1080i), and it is also suitable for general video. Therefore, the selected interface needs to complete the transmission of high-speed code stream source files and is easy to plug and unplug. The USB interface just meets these two conditions. High-quality source files have a large amount of data and require high transmission interfaces. And in the simulation environment of the FPGA, the USB interface also has to undertake the task of returning the decoding result to the PC host computer. This requires that the transmission speed be at least guaranteed to exceed the decoding speed. Compared with the USB 1.1 interface, the transmission of the USB 2.0 interface is more in line with the requirements of this design.
According to calculations, the transmission interface requires a transmission rate of at least 30 MB/s to ensure decoding of 1080i images.
Device selection
The use of FPGAs for simulation and verification has become an essential part of the IC design process, especially for large-scale designs. The design of this decoder IC uses Virtex II FPGA as the simulation environment. For this design, the XC2V6000 in the FF1517 BGA package has fully met the design requirements. Under the premise of design cost, this FPGA is a relatively cost-effective choice.
Cypress's EZ-USB FX2 is an integrated USB 2.0 microprocessor that integrates a USB 2.0 transceiver, SIE (serial interface engine), enhanced 8051 microcontroller and programmable peripheral interface. This optimized design of the FX2 can achieve a data transfer rate of almost 56MB/s, while the maximum bandwidth allowed by USB 2.0 is 480Mb/s, which is 60MB/s. The chip adds many integrated control functions with minimal impact on the transmission bandwidth. The GPIF and Slave FIFO modes provide a simple and seamless interface to external FPGAs, DSPs, and ATAs.
System architecture
The main body of this design is shown in Figure 1. In the FPGA simulation platform, Virtex II includes the decoder body and the interface module of the FPGA. The USB 2.0 chip 68013A acts as a separate part and is responsible for USB data transfer between the FPGA and the PC. The off-chip SRAM and DRAM are used as the extended storage device of the FPGA to store the source files required by the decoder, the decoded files, and the software program files used in the decoder.
Figure 1 Schematic diagram of FPGA simulation transmission
In this design, the decoder side has powerful functions and a CPU embedded in it. The ability to actively recognize commands can be performed. Therefore, the PC side and the decoder are in a peer position. The work of the PC side includes sending a command header, sending a command, transmitting a code stream, receiving a return decoding result, etc.; the work of the FPGA side includes receiving and identifying a command header and a PC command, receiving and storing a code stream into the SRAM and the DRAM, and reading the SRAM and the The decoding result in the DRAM is returned to the PC.
USB 2.0 chip working mode and firmware writing
1 Determination of the working mode of the chip
In the design, there are two processes involved in the transmission of large-scale data files: the PC transmits the source file downwards, and the FPGA transmits the decoding result file to the upper PC. It has the highest requirements for USB transmission. If the transmitted source file cannot adapt to the decoding speed, it will cause the decoder to pause; if the return decoding result lags, the untransferred decoding result will be overwritten. The occurrence of any kind of situation will directly lead to the decoder failing to work.
In the case of high transmission requirements, the BULK (Batch Transfer) mode of the Slave FIFO provided by EZ-USB FX2 is used to meet the transmission requirements. In this mode, the USB chip memory unit is divided into six endpoints, hereinafter referred to as EP. EP0 and EP1 are reserved as chip configuration FIFOs. EP2, 4, 6, and 8 can be transmitted as users, and four EPs are organized in a double FIFO manner.
For example, as shown in Figure 2, the USB performs an OUT transfer, setting the EP2 endpoint to a 512-byte dual FIFO. In the external device's view, the USB terminal can continue to send data as long as it has a 512-byte FIFO that is "half full". When the FIFO of the operation is "full", the FX2 automatically converts it to the external interface, eliminating waiting for reading; and transferring the next "empty" FIFO in the USB interface queue to the USB interface for it to continue writing data. . The external interface is similar to this, as long as one FIFO is "half full", you can continue to read data. When the current operating FIFO reads "empty", FX2 automatically converts it to the USB interface, eliminating the waiting for writing and transferring the next "full" FIFO in the external interface queue to the interface for use by external devices.
Figure 2 EndPoint schematic
Figure 3 shows the working process of the dual FIFO. When a 512-byte FIFO is full, the FPGA can fetch the data inside, and the PC can write data to another FIFO (a set of solid arrows). When a 512-byte FIFO is empty, the PC can write data. At the same time, the FPGA can read another FIFO (a set of dashed arrows) that still has data.
Figure 3 Dual EP mode of operation
2 firmware programming
The following important configuration registers need to be set during the initialization of the USB device by writing a firmware program.
IFCONFIG; Set the USB clock to be provided externally and use the Slave FIFO mode.
EPXCFG (X=2, 4, 6, 8); configures four EP (endpoint FIFO) modes.
EPXFIFOCFG (X=2, 4, 6, 8); configures the automatic transmission mode of 4 EPs and the transmission bit width.
Some Other registers can be configured separately according to actual needs. In this design, EP2 is configured to transmit command headers, EP4 is used to transmit source files, EP6 is used to transmit commands, and EP8 is used to transmit decoded result files.
After the firmware program is designed, you can use the Control Panel that comes with FX2 to download the firmware program to the 68013A chip, or store it in an external I2C, so that the chip can read it itself the next time it is reset.
3 circuit design schematic
Figure 4 is a schematic diagram of the circuit design of the design. The originals are in the order from left to right: CY7C68013A chip, power coupling capacitor bank, USB 2.0 standard interface, standard RS232 serial port, external crystal oscillator and HIN232 serial chip. This design is based on this circuit schematic diagram to create a circuit board diagram to complete the USB 2.0 function.
Figure 4 circuit design schematic
Design of decoder and USB interface module on FPGA
In the SLAVE FIFO mode, the FPGA can actively decide whether it is necessary to read the data in the USB internal FIFO, not just passively accept the data sent by the PC. As shown in FIG. 5, the control modes: SLOE, SLRD, and SLWR are used as EP read/write signals and enable control signals. FIFOADR[1:0] is used as the selection signal of 4 EPs, that is, the target EP of the current operation is selected. PKTEND is the control terminal for the FPGA to actively command the USB chip to send data to the upper PC. FLAGX (X=A, B, C, D) indicates the empty information of the currently selected FIFO. The FD (8-bit or 16-bit) is a bidirectional data transmission port. The FPGA interface controls these ports for the purpose of operating the USB.
Figure 5 decoder and USB interface
In the FPGA interface, the design also defines a FIFO (internal FIFO) with a depth of 256 and a width of 32 bits. The reason is that the SRAM and DRAM parts of this design are constantly being called by the decoder, which results in the storage unit being occupied. At this time, the USB cannot operate on the storage unit. Therefore, in the FPGA interface, multiple USB transmitted data FDs (8 or 16 bits) are first spliced ​​into 32-bit data and stored in the internal FIFO. When the SRAM and DRAM are idle, they are transmitted to it. Such processing makes the USB transmission independent of the working state of the storage unit, and further increases the speed of the USB transmission to meet the transmission requirements.
Design verification and results analysis
After developing the USB driver under the Windows operating system, the design successfully used the EZ-USB chip and the Virtex II FPGA to complete the video data transmission. And in the FPGA working below the frequency of 66MHz, the real-time transmission and decoding of H.264 format video is completed. In the detection of transmission rate, USB can transmit data in large quantities up to 33MB/s, which fully adapts to the requirements of the decoder.
Design Analysis: This design utilizes a two-stage FIFO to fully exploit the speed advantages of USB 2.0. The design solution removes the bottleneck in the transmission and decoding process and achieves a seamless connection. The downside is that due to the Slave FIFO mode limitation of the USB chip, the PC and the decoder must directly communicate using command interaction, occupying a certain bandwidth. In a state where the command is too frequent, the efficiency is not high, but the impact on large-volume data transmission is small.
Conclusion
It is successful under the verification platform, and it is actually tested with source files of various compression ratios, achieving an average rate of 33MB/s and a maximum of 40MB/s. Completed and exceeded design requirements.
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