USB reading device and host computer design

Data acquisition occupies an irreplaceable position in information processing systems. It is based on sensors, signal measurement and processing, and microcomputers. It mainly studies the collection, storage, processing, and control of information data. Strong practicality. Data acquisition technology has been widely used in many fields such as radar, communication, underwater acoustics, remote sensing, speech processing, intelligent instrumentation, industrial automation, and biomedical engineering. The data collector generally includes a data acquisition portion and a data processing transmission portion. The former includes filtering, amplifying, sampling, holding, converting, and storing parts of the signal, and the latter includes data reading, transmission, and computer interface parts.

1 system structure and hardware circuit design

1.1 System block diagram and working principle

The system is mainly composed of four modules: FLASH memory module, FPGA control module, USB interface control module and power module. As shown in Figure 1.

The working principle is: the FLASH module stores data as a data source of the recorder; the FPGA module acts as a controller of the reading device, reads the FLASH data and transmits it to the USB control interface module; the USB control chip receives the command from the upper computer, and Communicate with the FPGA to perform the operations required by the user; the power module provides a stable power supply for each module.

1.2 Power Management Module

The operating voltage of the chip in this system is 5 V, 3.3 V, 2.5 V. Since the USB interface of the computer can supply 5 V power and the maximum current is 500 mA, it is enough for this system, so the 5 V power supply of this system is directly powered by USB, and the 5 V power supply is adjusted by the voltage regulator AMS1117 to 3.3 V. And 2.5 V power supply.

1.3 FPGA Module

The FPGA of this design uses XC2S50 of XILINX's Spartan-2 series, including FPCA configuration circuit and FPGA clock circuit and interface configuration.

The configuration of the FPGA is flexible. According to whether the chip can actively load the configuration data and the bit width of the bit stream, the main frame mode is used to configure the FPCA, as shown in Figure 2. A resistor is connected to each port on the output port of the FPGA to function as a coupling current limit, so that the external interface is matched with the FPGA to prevent the battery from being burnt out due to excessive current and other adverse effects.

1.4 USB interface module

Generally, the types of USB interface chips can be roughly divided into: a main controller, a root hub, an interface chip, and a microcontroller having a USB interface. This design utilizes the CY7C68013A-128PIN chip of the EZ-USB FX2LP series.

This design uses 0XC0 EEPROM boot mode. That is, the first byte in the EEPROM is written to 0XC0, and the VID, PID, DID, and configuration bytes are written to the EEPROM. After the chip is powered on, the data is copied to the on-chip memory and sent to the host, and the host selects an appropriate firmware program to download to the USB chip according to the ID data. This design uses a serial EEPROM chip AT24C64 with an I2C bus interface. The AT24C64 has a capacity of 8192 x 8 bits and can be erased 1 million times.

1.5 FLASH memory module

The FLASH memory stores the data of the recorder. The purpose of this design is to read the data from the FLASH and transfer it to the computer for storage. This design uses SAM9UNG's K9F5608UO D NAND FLASH memory. Its characteristics are as follows: the memory cell array is (32M + 1024k) bit & TImes; 8bit; a total of 64k blocks, each block contains 32 pages, each page is 512 + 16 bytes; page-based programming (200μs typical programming time), Block is unit erase (2ms typical erase time); command, address, data multiplexing port; provides hardware data protection.

The hardware connection circuit of this design is shown in Figure 3. The MAX1658 provides power to the K9F5608UOD, and the rejection acts as a coupling current limit.

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