Low-cost MP3 player system integration technology

Although MP3 players are portable multimedia (PMP) devices, the integration technology is relatively simple. However, this simplicity comes from the powerful functions of the SoC processor, which simplifies the originally complicated work of the engineer. This article will introduce the low-cost, simple-function MP3 player system integration technology.

Although MP3 players are portable multimedia (PMP) devices, the integration technology is relatively simple. However, this simplicity comes from the powerful functions of the SoC processor, which simplifies the originally complicated work of the engineer. Of course, to obtain such simplicity and convenience, it is necessary to pay a price-must pay the SoC processor and operating system software license and royalties. This is like the PC solution of the Wintel Group. Although it is easy to develop and can be mass-produced early, its core technical knowledge (know-how) is similar to closed and undetectable.

Functional unit

Low-cost, simple-function MP3 players require at least the following basic units: processor / microcontroller, MP3 decoder, DMA, memory, hard disk, power supply circuit, DAC or I2S, LCD and keyboard are options. Of course, you need an external speaker. In order to reduce the number of components, increase the flexibility of the design, and reduce the size, FPGAs can be used to design DMA, memory controllers, and IDE controllers. As shown in the attached (Figure 1).

Figure 1 The internal functional unit of a low-cost MP3 player

FPGA circuit

In the FPGA circuit in Figure 1, the most important functions are listed as follows:
● Main circuit: This is the complete data path-from the microcontroller bus to the shared parameter / address mapping memory, to the DRAM / IDE bus. It contains all external buffers that the microcontroller can access, event detection (event detecTIon) and mobile request bits (acTIon request bits). The external buffer group is located in the DRAM and performs various specific tasks; when the power is turned off, these buffers will disappear. The event detection and movement request bits are to let the microcontroller know the current status and take appropriate movements or execute specific firmware programs.

● State machine for control: responsible for receiving various movement request bits, and validating all control lines, and finally causing data movement. It is a simple, but large state machine; usually it is in an idle and waiting state until a move is to be taken. All states are named using S_state_ #. Under the proper condition, the OR gate will make the correct control signal take effect, as shown in the second figure. This circuit also contains a "priority encoder". In the idle state, if many requests are shelved, the priority encoder can decide which one to execute first. Although this circuit is a bit complicated, it uses the simple concept of "one-hot". The so-called "one hot" means that each state is realized using a flip-flop. In each state, only one flip-flop is at a high value, and the rest are low values, and the "hot" (Hot bit) "will keep moving until it returns to the idle state. On the DMA path, there is a flip-flop (can also be omitted). When the condition for ending the DMA operation is established (ISZERO), this flip-flop will receive a "hot bit". All control signals are generated by the OR gate. As long as one of the input status signal groups is a high value, the OR gate will output a high value (make the control signal effective). For example: if the S_RD_IDE_1 or S_WR_IDE_1 of OR2 (Figure 2) is a high value, the output of IDE_ADDR will also be a high value, so IDE_ADDR takes effect. However, there are some time-critical (TIming criTIcal) signals that are not generated using OR gates. They are generated using set / reset buffers. The function of creating / resetting the buffer is the same as the OR gate, but there is no delay.

Figure 2 OR gate function in state machine

â–  Microcontroller bus MOVX detection Listen to the microcontroller bus, when there is no MOVX instruction to be executed, make the DMA_OK signal effective. When DMA_OK is not in effect, the priority encoder will not allow any non-CPU hardware unit to access the DRAM. Therefore, it responds to the microcontroller's read and write requests immediately without delay. This is very important for the 8051 microcontroller, because the 8051 has no wait state. If a MOVX operation code is detected, but MOVX is not executed, a 31-cycle timer can make DMA_OK effective again.

■ Address decoding of the microcontroller After these signals become effective, the external buffer can be used in the memory image area of ​​the microcontroller. Usually, this is to combine the address cable with the REG_RD signal or REG_WR signal; the REG_RD and REG_WR signals are generated by the state machine.

â–  DRAM / IDE address multiplexer (mux)
Switch between DRAM / IDE address bits (from the microcontroller) and DRAM / IDE address pins (or from the microcontroller); or zero, when performing direct transfer operations of IDE DMA ( Similar to PIO).

â–  MP3 output shift register (shift register)
This is a 16-bit shift register. It gets a 16-bit word from the IDE interface and sends this word to the MP3 decoder in a shifted manner.

â–  The MP3 bit counter counts the number of bits sent by the shift register to the MP3 decoder. When all 16 bits are shifted out, a signal is generated. At this time, the shift register is ready to be used by STA013 DMA to continue reading and transferring the next block from DRAM.

■ DRAM refresh clock This circuit will generate a pulse every 15.2 μs, requiring the state machine to perform a DRAM refresh cycle. This pulse will establish a request flag in the main circuit. When the bus is available, the state machine will start to perform the reset operation, and the request with a higher priority will not be shelved.

â–  DRAM / IDE address buffer (buffer)
Save the address, these addresses are used to drive the DRAM and IDE interface.

■ The 32-byte SRAM memory uses two 16 × 16 width DRAM memories, virtualizing them into SRAMs with address or data latch functions. One of them holds the page number of DRAM. These pages are mapped to the address space 0xFF00 to 0xFF1F of the microcontroller (DRAM_PAGE_CFG buffer). They are sent to the DRAM / IDE together with the 12 address bits of the microcontroller The address multiplexer can finally generate a unique address for DRAM read and write operations. The second SRAM is responsible for saving the DMA parameter values ​​(in the area of ​​0xFF20 to 0xFF3F). The external memory (DRAM) space image of the microcontroller is shown in the attached (Table 1).

Table 1 Microcontroller external memory (DRAM) space map

■ The write function of the address-mapped memory takes effect and allows write operations to the address-mapped memory. However, it only allows the microcontroller to write data in the memory area of ​​0xFF00 to 0xFF1F.

â–  The write function of the DMA parameter memory takes effect and allows write operations to the DMA parameter memory. The microcontroller can write these parameters, and these parameters can also be updated by the state machine, for example: the state machine can change them when performing DMA transfer operations.

â–  16-bit increment / decrement circuit When performing DMA transfer operation, 16-bit increment / decrement can be used to update the parameter value. The increment circuit is to calculate the target address of the DRAM, and the decrement circuit is to calculate the word group. The output value of the DMA parameter memory will be sent to this circuit, and will also be sent to 16 multiplexers to allow DMA parameters to be translated into addresses as if they came from the address bus of the microcontroller )same.

â–  Zero, One and Odd Value Detector When the DMA parameter value is changed, this circuit can immediately know; if the DMA parameter value is zero, one or odd address, this circuit can also notify the state machine. When the DMA parameter value is zero, the state machine clears the DMA request flag to terminate the DMA operation and sets the "complete DMA transfer" interrupt flag to 1.

â–  The synchronization of the "address latch enable (ALE)" signal of the microcontroller can synchronize the ALE signal of the microcontroller with the clock of the FPGA. The other control signals of the microcontroller also use a similar synchronization mechanism, but they are located in the main circuit.

â–  2: 1 multiplexer / 4 bits This circuit allows addresses in every 32 byte memory to be controlled by the general function of the memory or by the bus of the microcontroller (when the firmware reads from these registers or Write, to change the address map or establish a DMA transfer).

■ 2: 1 multi-tasker / 8 bits It is used in IDE block. It allows data to be loaded into the output buffer from the data area of ​​the microcontroller.

â–  2: 1 multi-tasker / 16 bit When performing a DMA cycle, this circuit can be used to switch from the address bus (general operation) of the microcontroller to the address bus of the DMA parameter memory.

■ 2: 1 multi-tasker / 16-bit use this circuit to select the input value of the DMA parameter memory; it is the updated DMA parameter (within a DMA cycle) and the microcontroller ’s data bus (when the microcontroller writes DMA settings). The 16-bit multi-tasker is designed separately because the image of the "configurable logic block (CLB)" of the FPGA development tool cannot incorporate additional logic gates into the 2: 1 more than those listed above In the tasker (this will waste 8 CLBs and add extra delay time on the important timing path) unless the logic gates are in the same circuit design diagram.

â–  16 to 8-bit bus, tri-state (tri-state) buffer This tri-state buffer allows any nibble (8 bit) of a 16-bit bus to drive an 8-bit bus. It allows the microcontroller to read data from a 16-bit wide memory.

â–  The 8 to 16-bit bus buffer connects two 8-bit buses to become a 16-bit bus (but FPGA development tools are not to be confused).

â–  An 8 to 16-bit bus buffer connects an 8-bit bus twice to become a 16-bit bus (but FPGA development tools are not to be confused by this). Any nibble of this 16-bit bus comes from this 8-bit bus, as attached (Figure 3).

Figure 3: 8 to 16-bit bus buffer

â–  8-bit buffer An 8-bit buffer is used to collect the address bits of the microcontroller.

In addition, due to the performance differences of different FPGA development tools, you may also need to:
● Several displacement registers with different number of bits (for example: 5 to 9 bits): they are used in the state machine. You can avoid having FPGA development tools crash because there are too many symbols in the same circuit design.
● Flip-flop (in CLB): This is the only CLB flip-flop, redesigned with a smaller symbol than in the FPGA development link library (library).
● flip-flop (in IOB): This is the only "I / O block (IOB)" flip-flop, redesigned with a smaller symbol than in the FPGA development link library (library).

FPGA circuit can be regarded as a more complicated part of this MP3 player system. General OEM / ODM can designate outsourcing specifications. Another OEM / ODM manufacturer must pay attention to the design of the firmware; perhaps the firmware can also be outsourced, but they must understand how to use the application program interface (API) provided by the underlying firmware (assembly language) to design the upper layer User program (C language program).

Application program interface

The application program interface includes at least: dynamic configuration memory (memory allocation), file / directory reading, MP3 music playback, communication with other peripherals (including: serial port that can be used for debugging purposes, LCD display ... Wait). Here only introduces the application program interface for dynamically configuring memory as follows:

â–  Dynamic configuration memory For user programs, it is necessary to configure memory to store character strings, structures, or other items. Its function is just like malloc () in C language. The simm_malloc () is used here, and its original formula is as follows:

● simm_id simm_malloc (unsigned int num_bytes):
Allocate num_bytes of DRAM memory space and return simm_id to represent this space. simm_id is not a pointer, but a number. To get the configured actual memory space address, you must use the addrX function, as shown below:
● xdata void * addr5 (simm_id addr32): map to 0x5000 ~ 0x5FFF
● xdata void * addr6 (simm_id addr32): map to 0x6000 ~ 0x6FFF
● xdata void * addr7 (simm_id addr32): map to 0x7000 ~ 0x7FFF

Map the memory space represented by simm_id to the address space of the microcontroller, and return an indicator. The return value of these functions is almost "typecast (typecast)", for example: (xdata char *) addr5 (string_id). Each function is mapped to a special section that belongs to the address space of the microcontroller. If any of the indicators has been used, this special section is not valid; therefore, for the same simm_id, only 3 different indicators can be obtained through the 3 functions listed above, and they cannot Is used, such an address space is valid.

To free the previously configured memory space of simm_malloc (), you must use the following function:
void simm_free (simm_id addr32)

In Table 1, the area from 0x0000 to 0xEFFF is the page for storing data, and the rest are buffers. Each page (or block) size is 4K (Bytes). The supported DRAM module size is from 1024 (4MBytes) to 8192 (32MBytes) blocks. After the system is initialized, these 4K large blocks will be configured and free. When a group of blocks is configured, usually the number of the first block will be used first, and the subsequent blocks are accessed sequentially by calling the next_block () function. The DRAM controller allows any 15 blocks to be mapped into the microcontroller's address space, from 0x0000 to 0xEFFF. The following items list the functions related to paging management (written in assembly language):

● init_memory_mgr: Initialize the "memory manager". It will detect the size of the DRAM module, and a small number of memory blocks will be reserved for the design of a linked list of all blocks. This link can serially track which blocks are idle and which are used. When the application requires a set of blocks, the reserved memory block will store the serial of the set of blocks. This function must be called before using other functions.
● malloc_blocks: configure one or more blocks (4K large paging), and return the number of the first block. If you want to configure more than one block, you must use the next_block function to extract other blocks. Please note that, like simm_malloc (), these blocks are not automatically mapped into the addressing space of the microcontroller.
● map_block: Map a block to the addressing space of the microcontroller. Enter the page number (0 ~ 14) and the number of blocks.
● free_blocks: release the configured blocks. The mapping of the released block will not disappear automatically. Enter the number of the first block, and the blocks in the same group will be released.
● next_block: used with malloc_blocks when retrieving more than one block. Enter the number of the current block and it will return the number of the next block.

Conclusion

For many small and medium-sized electronics companies, the cost of using SoC processors and operating system software to develop PMP products is relatively high. "Low cost" seems to be just an ideal, because when the cost of components decreases, the cost of integrated technology may rise. Integration technology requires many different technologies and knowledge. It is like designing an SoC processor. If you want to find talents specializing in various technical fields, you will inevitably increase personnel costs. (This article was originally published in the 164th issue of Component Magazine)