Abstract: The Dallas Semiconductor framers can operate in a transparent mode in both the receive and transmit direcTIons. The transmitter will not insert framing, signaling, or other informaTIon such as CRC or FDL. Generally, the receive side of the framers is always transparent. Data received at RTIP and RRING is passed through intact to RSER. All configuraTIons are with the elastic stores disabled. The elastic stores will not alter data except during slip conditions or if configured for 1.544MHz / 2.048MHz conversion or signaling reinsertion.
IntroductionThis application note applies to the following products.
The Dallas Semiconductor framers can operate in a transparent mode in both the receive and transmit directions. The transmitter will not insert framing, signaling, or other information such as CRC or FDL. Generally, the receive side of the framers is always transparent. Data received at RTIP and RRING is passed through intact to RSER. All configurations are with the elastic stores disabled. The elastic stores will not alter data except during slip conditions or if configured for 1.544MHz / 2.048MHz conversion or signaling reinsertion.
Transparent Operation on DS21Q42, DS21FF42, DS21FT42, DS21352, DS21552, DS21Q352, DS21Q552Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h TCC1, TCC2, TCC3 = 00h RCC1, RCC2, RCC3 = 00h TDC1.7 = 0 CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS21Q44, DS21FF44, DS21FT44, DS21354, DS21554, DS21Q354, DS21Q554Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 TCR2.1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCC1, TCC2, TCC3, TCC4 = 00h RCC1, RCC2, RCC3, RCC4 = 00h TSaCR = 00h TDC1 .7 = 0 Transparent Operation on DS2152Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h TCC1, TCC2, TCC3 = 00h RCC1, RCC2, RCC3 = 00h CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS2154Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 TCR2.1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 CCR4.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCC1, TCC2, TCC3, TCC4 = 00h RCC1, RCC2, RCC3, RCC4 = 00h Transparent Operation on DS2155, DS2156, DS21455, DS21458 and DS21Q55 for E1 ModeRegister Configurations:
MSTRREG = 02h T1RCR1 = 00h, T1RCR2 = 00h T1TCR1 = 00h, T1TCR2 = 00h T1CCR1 = 00h E1RCR1 = 00h, E1RCR2 = 00h E1TCR1 = 80h, E1TCR2 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR3 = 00h, CCR3 = 00h, CCR2 = 00h, CCR3 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, = 00h, H2TC = 00h Transparent Operation on DS2155, DS2156, DS21455, DS21458 and DS21Q55 for T1 ModeRegister Configurations:
MSTRREG = 00h T1RCR1 = 1Eh, T1RCR2 = 60h T1TCR1 = 60h, T1TCR2 = 80h T1CCR1 = 04h E1RCR1 = 00h, E1RCR2 = 00h E1TCR1 = 00h, E1TCR2 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR2 = 00h, CCR2 = 00h = 00h, H2TC = 00h Transparent Operation on DS21Q50 for E1 ModeRegister Configurations:
RCR1 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR4 = 00h CCR5 = 00h TIR1 = 00h, TIR2 = 00h, TIR3 = 00h, TIR4 = 00h Transparent Operation on DS2151, DS21Q41Hardware Considerations:
TSER and TLINK must be tied together either logically or physically.
Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS2153, DS21Q43Hardware Considerations:
Need rev A5 or better for complete receive transparency with elastic store enabled (DS2153 only).
Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCR2 .1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 RCR2.1 = 0 (required on rev A2 devices only) In order to get transparent mode working on the devices DS26401, DS26521, DS26524 and DS26528, the customer should never set the RMMR and TMMR INIT_DONE bits to 1. Doing so will cause the framer to search for the framing pattern.
Transparent Operation on DS26401 for E1 ModeRegister Configurations:
RMMR = 81h RCR1 = 22h, RCR2 = 00h TMMR = 81h TCR1 = 80h, TCR2 = 00h Transparent Operation on DS26401 for T1 ModeRegister Configurations:
RMMR = 80h RCR1 = CAh, RCR2 = 0Ch TMMR = 80h TCR1 = 64h, TCR2 = 00h, TCR3 = 00h Transparent Operation on DS26521, DS26524 and DS26528 for E1 Mode Register Configurations:
RMMR = 81h E1RCR1 = 22h, E1RCR2 = 00h, E1RCR3 = 00h TMMR = 81h E1TCR1 = 80h, E1TCR2 = 00h, TCR3 = 00h Transparent Operation on DS26521, DS26524 and DS26528 for T1 ModeRegister Configurations:
RMMR = 80h T1RCR1 = CAh, T1RCR2 = 0Ch TMMR = 80h T1TCR1 = 64h, T1TCR2 = 00h, TCR3 = 00h ConclusionIf you have further questions about transparent operation on Dallas Semiconductor framers or SCTs, contact the Telecommunications Applications Support Team via email at var name = "telecom.support @"; var domain = "dalsemi.com"; document.write ("" + name + domain + ""); telecom. or call 972-371-6555.
or transmitted without host intervention.
The user must take care to not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode, map both controllers to the FDL. HDLC # 1 and HDLC # 2 are identical in operation and therefore, when applicable, each DS21x52 register bit will be mapped to two addresses.
DS21x52 Register: HCR: HDLC Control Register
DS21x52 Register Address: 00 Hex
HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. HxRC refers to H1RC and H2RC located at addresses 31 Hex and 32 Hex respectively. TABT, bit 3, has been incorporated into the Transmit HDLC Reset (THR) bit. DS21x52 Register: HSR: HDLC Status Register
DS21x52 Register Address: 01 Hex
The status bits for HDLC # 1 have been mapped to Status Register 6 (SR6) in the DS2155. The status bits for HDLC # 2 have been mapped to Status Register 7 (SR7) in the DS2155. THALF, bit 2, has been renamed to TLWM. In the DS21x52, THALF is set when the transmit 64-byte FIFO empties beyond the halfway point. For the DS2155, the TLWM bit will be set when the transmit 128-byte FIFO empties beyond the low water mark as defined by the TFLWM0-TFLWM2 bits located in the FIFO control register (H1FC, H2FC). The low water mark is programmable to one of 8 different levels. RHALF, bit 4, has been renamed to RHWM. In the DS21x52, RHALF is set when the receive 64-byte FIFO fills beyond the halfway point. For the DS2155, the RHWM bit will be set when the receive 128-byte FIFO fills beyond the high water mark as defined by the RFHWM0-RFHWM2 bits located in the FIFO control register (H1FC, H2FC). The high water mark is programmable to one of 8 different levels. DS21x52 Register: HIMR: HDLC Interrupt Mas k Register
DS21x52 Register Address: 02 Hex
The interrupt mask bits for HDLC # 1 have been mapped to HDLC Interrupt Mask Register 6 (IMR6) in the DS2155. The interrupt mask bits for HDLC # 2 have been mapped to HDLC Interrupt Mask Register 7 (IMR7) in the DS2155. THALF, bit 2, has been renamed to TLWM. When THALF is enabled in the DS21x52, the device will generate an interrupt when the transmit 64-byte FIFO empties beyond the halfway point. For the DS2155, the device will generate an interrupt, if TLWM is enabled, when the transmit 128-byte FIFO empties beyond the low water mark as defined by the TFLWM0-TFLWM2 bits located in the FIFO control register (H1FC, H2FC). The low water mark is programmable to one of 8 different levels. RHALF, bit 4, has been renamed to RLWM. When RHALF is enabled in the DS21x52, the device will generate an interrupt when the receive 64-byte FIFO fills beyond the halfway point. For the DS2155, the device will generate an interrupt, if RHWM is enabled, when the receive 128-byte FIFO fills beyond the high w ater mark as defined by the RFHWM0-RFHWM2 bits located in the FIFO control register (H1FC, H2FC). The high water mark is programmable to one of 8 different levels. DS21x52 Register: RHIR: Receive HDLC Information Register
DS21x52 Register Address: 03 Hex
The HDLC information bits for HDLC # 1 have been mapped to the Receive HDLC # 1 Information Register, INFO5. The HDLC information bits for HDLC # 2 have been mapped to the Receive HDLC # 2 Information Register, INFO6. OBYTE, bit 0, is renamed as H1OBT for HDLC # 1 and H2OBT for HDLC # 2. Both H1OBT & H2OBT can be found in the HDLC Event Information Register (INFO4, address 2D Hex). There is no new functionality associated with this bit. HxRPBA refers to H1RPBA and H2RPBA, located at addresses 9C Hex and AC Hex respectively. CBYTE, bit 1, has been renamed as MS. Unlike the operation of the CBYTE bit in the DS21x52, the MS bit will be low when the byte available for reading the receive FIFO is the last byte of a message. MS will be high when the byte available for reading is the first byte of the continuation of a message. POK, bit 2, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RVM, bit 4, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. ROVR, bit 5, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RCRCE, bit 6, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RABT, bit 7, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. DS21x52 Register: RBOC: Receive Bit Oriented Code Register
DS21x52 Register Address: 04 Hex
BOC0-BOC5, bits 0-5, share the RFDL register in the DS2155. See section 22 of the DS2155 for additional information on the BOC controller.DS21x52 Register: RHFR: Receive HDLC FIFO
DS21x52 Register Address: 05 Hex
The Receive HDLC FIFO Register has been relocated to address 9E Hex for HDLC # 1 and AE Hex for HDLC # 2. The lower 7 bits of the Receive Packet Bytes Available registers (H1RPBA, H2RPBA) indicate the number of bytes that can be read from the receive FIFO. The value indicated by the lower seven bits in these registers informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC Information register for detailed message status. See section 24.4 .2 of the DS2155 data sheet for additional information. DS21x52 Register: THIR: Transmit HDLC Information Register
DS21x52 Register Address: 06 Hex
TUDR, bit 0, is renamed as H1UDR for HDLC # 1 and H2UDR for HDLC # 2. Both H1UDR & H2UDR can be found in the HDLC Event Information Register (INFO4, address 2D Hex). There is no new functionality associated with this bit . DS21x52 Register: TBOC: Transmit Bit Oriented Code Register
DS21x52 Register Address: 07 Hex
BOC0-BOC5, bits 0-5, share the TFDL register in the DS2155. See section 22 of the DS2155 for additional information on the BOC controller. HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. HBEN, bit 6, has been renamed as THMS. The THMS bit behaves in a different manner than the HBEN bit. See section 22 and 24 of the DS2155 for more information about the HDLCs operation. DS21x52 Register: THFR: Transmit HDLC FIFO
DS21x52 Register Address: 08 Hex
The Transmit HDLC FIFO Register has been relocated to address 9D Hex for HDLC # 1 and AD Hex for HDLC # 2. The Transmit FIFO Buffer Available registers (H1TFBA, H2TFBA) indicate the number of bytes that can be written into the transmit FIFOs. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer DS21x52 Register: RDC1: Receive HDLC DS0 Control Register 1
DS21x52 Register Address: 90 Hex
RD0 through RD4, bits 0 to 4, and RDS0M, bit 5, have been replaced by registers H1RCS1 to H1RCS4 for HDLC # 1 and H2RCS1 to H2RCS4 for HDLC # 2. Any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel (s) any combination of bits within the channel (s) can be avoided. See section 24.3 of the DS2155 for additional information on mapping the HDLC data to channels. HxRC refers to H1RC and H2RC located at addresses 31 Hex and 32 Hex respectively. RDS0E, bit 7, has been renamed to RHMS. The operation of this bit is inverted from that of the DS21x52. See section 24 of the DS2155 for additional information. DS21x52 Register: RDC2: Receive HDLC DS0 Control Register 2
DS21x52 Register Address: 91 Hex
Receive HDLC DS0 Control Register 2 has been relocated to 96 Hex for HDLC # 1 and A6 Hex for HDLC # 2. DS21x52 Register: TDC1: Transmit HDLC DS0 Control Register 1
DS21x52 Register Address: 92 Hex
TD0 through TD4, bits 0 to 4, and TDS0M, bit 5, have been replaced by registers H1TCS1 to H1TCS4 for HDLC # 1 and H2TCS1 to H2TCS4 for HDLC # 2. Any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel (s) any combination of bits within the channel (s) can be avoided. See section 24.3 of the DS2155 for additional information on mapping the HDLC data to channels. HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. TDS0E, bit 7, has been renamed to THMS. The operation of this bit is inverted from that of the DS21x52. See section 24 of the DS2155 for additional information. DS21x52 Register: TDC2: Transmit HDLC DS0 Control Register 2
DS21x52 Register Address: 93 Hex
Transmit HDLC DS0 Control Register 2 has been relocated to 9B Hex for HDLC # 1 and AB Hex for HDLC # 2. DS21x52 Register: RFDL: Receive FDL Register
DS21x52 Register Address: 28 Hex
The Receive FDL Register has been relocated to address C0 Hex. The RFDL register will operate as the receive BOC message and information register when the receive BOC function is enabled by setting BOCC.4 to 1. The lower six bits of the RFDL register will contain the BOC message bits when used in this configuration. See section 22 of the DS2155 data sheet for more information. DS21x52 Register: RFDLM1, RFDLM2: Receive FDL Match Registers
DS21x52 Register Address: 29 & 2A Hex
Receive FDL Match Registers 1 and 2 have been relocated to address C2 Hex and C3 Hex, respectively. DS21x52 Register: TFDL: Transmit FDL Register
DS21x52 Register Address: 7E Hex
The Transmit FDL Register has been relocated to address C1 Hex. The TFDL register will operate as the transmit BOC message register when the transmit BOC function is enabled by setting BOCC.0 to 1. The lower six bits of the TFDL register will contain the BOC message to be transmitted. See section 22 of the DS2155 data sheet for additional information. Line Interface, Programmable In-Band Loop Code, and Transmit Transparency Registers DS21x52 Register: LICR: Line Interface Control Register
DS21x52 Register Address: 7C Hex
DS21x52 Register: IBCC: In-Band Code Control Register
DS21x52 Register Address: 12 Hex
DS21x52 Register: TCD: Transmit Code Definition Register
DS21x52 Register Address: 13 Hex
DS21x52 Register: RUPCD: Receive Up Code Definition Register
DS21x52 Register Address: 14 Hex
DS21x52 Register: RDNCD: Receive Down Code Definition Register
DS21x52 Register Address: 15 Hex
DS21x52 Register: TTR1, TTR2, TTR3: Transmit Transparency Registers
DS21x52 Register Address: 39, 3A, 3B Hex
The DS2155's programmable in-band loop code generation and detection includes support for 16-bit codes. In adding this feature a second register has been added for transmit code definition and receive up / down code definition. For generation or detection of 8 bit patterns, both of the appropriate definition registers must be filled with the same value. See section 26 of the DS2155 data sheet for additional information. Interleaved PCM Bus Operation Register The interleave bus operation has been converted to full software control in the DS2155 and the external pins associated with this option have been reassigned to the extended system information bus function. See section 29 for more detail on the interleaved PCM bus operation.
DS21x54 Register: IB Interleaved Bus Operation Register
DS21x54 Register Address: 94 Hex
MSEL0 and MSEL1 are not included in the DS2155. INTSEL, bit 2, has been renamed IBOSEL. There is no new functionality associated with this control bit. 3. Software Considerations: DS2155 vs. DS21x54 (E1) This section will present the registers for the DS21354 and DS21554. The registers are presented in the order that they appear in the DS21354 and DS21554 data sheet.
ID RegisterDS21x54 Register: IDR: Device Identification Register
DS21x54 Register Address: 0F Hex
The Device Identification Register (IDR) for the DS2155 is located at the same address as the IDR for the DS21x54. The upper four bits display the DS2155 ID (1011) and the lower four bits display the die revision. Receive Control Registers DS21x54 Register: RCR1 : Receive Control Register 1
DS21x54 Register Address: 10 Hex
RSM, bit 6, has been renamed as RSMS1. There is no new functionality associated with the bit. RSDW, bit 7, has been renamed as RSMS2. There is no new functionality associated with the bit. DS21x54 Register: RCR2: Receive Control Register 2
DS21x54 Register Address: 11 Hex
RBCS, bit 2, has been renamed as RSCLKM. There is no new functionality associated with the bit. Transmit Control Registers DS21x54 Register: TCR1: Transmit Control Register 1
DS21x54 Register Address: 12 Hex
DS21x54 Register: TCR2: Transmit Control Register 2
DS21x54 Register Address: 13 Hex
PF, bit 0, has been renamed as RLOSF. There is no new functionality associated with the bit. Common Control Registers DS21x54 Register: CCR1: Common Control Register 1
DS21x54 Register Address: 14 Hex
RSM, bit 3, has been renamed as RSIGM. There is no new functionality associated with the bit. DS21x54 Register: CCR2: Common Control Register 2
DS21x54 Register Address: 1A Hex
LOTCMC, bit 2, has been combined with other functions to simplify the selection of the transmit clock source. The two bits, Transmit Clock Source Select 0 (TCSS0) and Transmit Clock Source Select 1 (TCSS1), are located in the DS2155's Common Control Register 1 (CCR1, address 70 Hex) in bit positions 1 and 2 respectively. DS21x54 Register: CCR3: Common Control Register 3
DS21x54 Register Address: 1B Hex
TBCS, bit 1, has been renamed as TSCLKM. There is no new functionality associated with this bit. THSE, bit 2, has been renamed as THSCS. See sections 7 and 17 of the DS2155 data sheet for information on per-channel register operation . RSRE, bit 3, has been renamed as RSRCS. See sections 7 and 17 of the DS2155 data sheet for additional information on receive signaling re-insertion. Control bit 5, TIRFS, has been incorporated in the new functionality for idle code generation. See section 18 of the DS2155 data sheet for more detail. Control bit 6, TCBFS, has been incorporated into the per-channel register operation. See sections 7 and 17 of the DS2155 data sheet for additional information. DS21x54 Register: CCR4: Common Control Register 4
DS21x54 Register Address: A8 Hex
LIAIS, bit 1, has been renamed as TUA1. There is no new functionality associated with this bit. DS21x54 Register: CCR5: Common Control Register 5
DS21x54 Register Address: AA Hex
TESA, bit 5, has been renamed as TESALGN. There is no new functionality associated with the bit. RESA, bit 6, has been renamed as RESALGN. There is no new functionality associated with the bit. DS21x54 Register: CCR6: Common Control Register 6
DS21x54 Register Address: 1D Hex
TCLKSRC, bit 2, has been combined with other functions to simplify the selection of the source for the transmit clock. Two bits, Transmit Clock Source Select bit 0 (TCSS0) and bit 1 (TCSS1) are located in the DS2155's Common Control Register 1 (CCR1, address 70 Hex) in bit positions 1 and 2 respectively. LIUSI, bit 5, has been renamed as RSCLKE. There is no new functionality associated with the bit. However, there is now a TSCLKE control bit available in the DS2155, which controls G.703 support for the transmitter. CDIG, bit 6, has been renamed as TAOZ. There is no new functionality associated with the bit. LIUODO, bit 7, has been renamed as CLDS. In the DS21x54, this bit determined whether the TTIP and TRING outputs would be open drain or not. In the DS2155, setting this bit to a one will redefine the operation of the transmit line driver. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1 .7 = 0, then the device will generate a square wave at the TTIP and TRING outputs instead o fa normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = 0 and LIC1.7 = 1, then the device will force TTIP and TRING outputs to become open drain drivers instead of their normal push-pull operation. This bit should be set to zero for normal operation of the DS2155. Status and Information Registers DS21x54 Register: RIR: Receive Information Register
DS21x54 Register Address: 08 Hex
RESE, bit 3, has been renamed as RESEM. There is no new functionality associated with this bit. TESE, bit 6, has been renamed as TESEM. There is no new functionality associated with this bit. DS21x54 Register: SSR: Synchronizer Status Register
DS21x54 Register Address: 1E Hex
The Synchronizer Status Register has been relocated to address 30 Hex in the DS2155. DS21x54 Register: SR1: Status Register 1
DS21x54 Register Address: 06 Hex
RCL, bit 1, has been renamed as LRCL. No additional functionality is associated with this bit. DS21x54 Register: SR2: Status Register 2
DS21x54 Register Address: 07 Hex
SEC, bit 5, has been renamed as TIMER. In the DS21x54, this bit was set on increments of one second (referenced to RCLK). In the DS2155, this bit follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). In T1 mode, this bit can be configured to set on increments of 1 second or 42ms (referenced to RCLK). DS21x54 Register: IMR1: Interrupt Mask Register 1
DS21x54 Register Address: 16 Hex
RCL, bit 1, has been renamed as LRCL. No additional functionality is associated with this bit. DS21x54 Register: IMR2: Interrupt Mask Register 2
DS21x54 Register Address: 17 Hex
SEC, bit 5, has been renamed as TIMER. In the DS21x54, this bit enabled the interrupt on increments of one second (referenced to RCLK). In the DS2155, this bit follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). In T1 mode, this bit can be configured to interrupt on increments of 1 second or 42ms (referenced to RCLK). Error Count RegistersThe error count registers have been kept intact, but have been relocated. In addition, all of the count registers are now 16-bit registers because the registers that were shared in the DS21x54 are no longer shared in the DS2155. See section 15 in the DS2155 data sheet for additional information on the error count registers.
DS21x54 Registers: VCR1, VCR2: Bipolar Violation Count Register 1 & 2
DS21x54 Register Address: 00, 01 Hex
DS21x54 Registers: CRCCR1, CRCCR2: CRC4 Count Register 1 & 2
DS21x54 Register Address: 02 Hex (Same as FASCR1), 03 Hex
DS21x54 Register: FASCR1, FASCR2: FAS Error Count Register 1 & 2
DS21x54 Register Address: 02 Hex (Same as CRCCR1), 04 Hex (Same as EBCR1)
DS21x54 Register: EBCR1, EBCR2: E-Bit Count Register 1 & 2
DS21x54 Register Address: 04 Hex (Same as FASCR2), 05 Hex
In the DS21x54, CRCCR1 and FASCR1 shared the count register located at address 02 Hex. The two error counters no longer share a register in the DS2155. Additionally, FASCR2 and EBCR1 shared the count register located at address 04 Hex. These two error counters no longer share a register in the DS2155. DS0 Monitoring Function Registers Both the Transmit DS0 Monitor Register and Receive DS0 Monitor Register has been relocated to a new address.
DS21x54 Register: TDS0M: Transmit DS0 Monitor Register
DS21x54 Register Address: A9 Hex
DS21x54 Register: RDS0M: Receive DS0 Monitor Register
DS21x54 Register Address: AB Hex
Signaling RegistersThe Transmit Signaling Registers and Receive Signaling Registers have been relocated to 50-5F Hex and 60-6F Hex, respectively. Additionally, the signaling information contained in the signaling registers has been rearranged. See section 17 of the DS2155 data sheet for additional information on signaling operation.
DS21x54 Register: RS1 to RS16: Receive Signaling Registers
DS21x54 Register Address: 30 to 3F Hex
The Receive signaling registers have been relocated to 60-6F Hex The following table shows the new the arrangement for the Receive Signaling Registers. Transmit Signaling Registers (T1 Mode, ESF Format)
DS21x54 Register: TS1 to TS16: Transmit Signaling Registers
DS21x54 Register Address: 40 to 4F Hex
Transmit Signaling Registers 1 through 16 can be found at addresses 50 Hex through 5F Hex. In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "Channel" numbering, TS0 through TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are labeled channel 15 through channel 30. See table 17-1 in the DS2155 for more information. The following tables show the new the arrangement for the Transmit Signaling Registers for CAS and CCS formats. Transmit Signaling Registers (E1 Mode, CAS Format)
Transmit Signaling Registers (E1 Mode, CCS Format)
Per-Channel Code Generation RegistersThe method for generating idle codes has changed in the DS2155. The DS2155 contains a 64-byte Idle Code Array accessed by t
IntroductionThis application note applies to the following products.
| T1 Framers | E1 Framers | T1 / E1 / J1 Framers | T1 SCTs | E1 SCTs | T1 / E1 SCTs |
| DS21Q41 | DS21Q43 | DS26401 | DS2151 | DS2153 | DS2155 |
| DS21Q42 | DS21Q44 | DS2152 | DS2154 | DS21Q55 | |
| DS21FF42 | DS21FF44 | DS21352 | DS21354 | DS2156 | |
| DS21FT42 | DS21FT44 | DS21552 | DS21554 | DS21455 | |
| DS21Q352 | DS21Q354 | DS21458 | |||
| DS21Q552 | DS21Q554 | DS26521 | |||
| DS2150 | DS26524 | ||||
| DS21Q50 | DS26528 |
The Dallas Semiconductor framers can operate in a transparent mode in both the receive and transmit directions. The transmitter will not insert framing, signaling, or other information such as CRC or FDL. Generally, the receive side of the framers is always transparent. Data received at RTIP and RRING is passed through intact to RSER. All configurations are with the elastic stores disabled. The elastic stores will not alter data except during slip conditions or if configured for 1.544MHz / 2.048MHz conversion or signaling reinsertion.
Transparent Operation on DS21Q42, DS21FF42, DS21FT42, DS21352, DS21552, DS21Q352, DS21Q552Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h TCC1, TCC2, TCC3 = 00h RCC1, RCC2, RCC3 = 00h TDC1.7 = 0 CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS21Q44, DS21FF44, DS21FT44, DS21354, DS21554, DS21Q354, DS21Q554Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 TCR2.1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCC1, TCC2, TCC3, TCC4 = 00h RCC1, RCC2, RCC3, RCC4 = 00h TSaCR = 00h TDC1 .7 = 0 Transparent Operation on DS2152Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h TCC1, TCC2, TCC3 = 00h RCC1, RCC2, RCC3 = 00h CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS2154Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 TCR2.1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 CCR4.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCC1, TCC2, TCC3, TCC4 = 00h RCC1, RCC2, RCC3, RCC4 = 00h Transparent Operation on DS2155, DS2156, DS21455, DS21458 and DS21Q55 for E1 ModeRegister Configurations:
MSTRREG = 02h T1RCR1 = 00h, T1RCR2 = 00h T1TCR1 = 00h, T1TCR2 = 00h T1CCR1 = 00h E1RCR1 = 00h, E1RCR2 = 00h E1TCR1 = 80h, E1TCR2 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR3 = 00h, CCR3 = 00h, CCR2 = 00h, CCR3 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, CCR2 = 00h, = 00h, H2TC = 00h Transparent Operation on DS2155, DS2156, DS21455, DS21458 and DS21Q55 for T1 ModeRegister Configurations:
MSTRREG = 00h T1RCR1 = 1Eh, T1RCR2 = 60h T1TCR1 = 60h, T1TCR2 = 80h T1CCR1 = 04h E1RCR1 = 00h, E1RCR2 = 00h E1TCR1 = 00h, E1TCR2 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR2 = 00h, CCR2 = 00h = 00h, H2TC = 00h Transparent Operation on DS21Q50 for E1 ModeRegister Configurations:
RCR1 = 00h CCR1 = 00h, CCR2 = 00h, CCR3 = 00h, CCR4 = 00h CCR5 = 00h TIR1 = 00h, TIR2 = 00h, TIR3 = 00h, TIR4 = 00h Transparent Operation on DS2151, DS21Q41Hardware Considerations:
TSER and TLINK must be tied together either logically or physically.
Register Configurations:
TCR1.2, TCR1.5, TCR1.6 = 1 TCR1.0, TCR1.1, TCR1.4 = 0 TCR2.0 = 0 TIR1, TIR2, TIR3 = 00h CCR1.5 = 0 RMR1, RMR2, RMR3 = 00h Transparent Operation on DS2153, DS21Q43Hardware Considerations:
Need rev A5 or better for complete receive transparency with elastic store enabled (DS2153 only).
Register Configurations:
TCR1.6 = 1 TCR1.2, TCR1.3, TCR1.4, TCR1.5 = 0 CCR1.4 = 0 CCR2.3, CCR2.4, CCR2.5 = 0 TIR1, TIR2, TIR3, TIR4 = 00h TCR2 .1, TCR2.2, TCR2.3, TCR2.4, TCR2.5, TCR2.6, TCR2.7 = 0 RCR2.1 = 0 (required on rev A2 devices only) In order to get transparent mode working on the devices DS26401, DS26521, DS26524 and DS26528, the customer should never set the RMMR and TMMR INIT_DONE bits to 1. Doing so will cause the framer to search for the framing pattern.
Transparent Operation on DS26401 for E1 ModeRegister Configurations:
RMMR = 81h RCR1 = 22h, RCR2 = 00h TMMR = 81h TCR1 = 80h, TCR2 = 00h Transparent Operation on DS26401 for T1 ModeRegister Configurations:
RMMR = 80h RCR1 = CAh, RCR2 = 0Ch TMMR = 80h TCR1 = 64h, TCR2 = 00h, TCR3 = 00h Transparent Operation on DS26521, DS26524 and DS26528 for E1 Mode Register Configurations:
RMMR = 81h E1RCR1 = 22h, E1RCR2 = 00h, E1RCR3 = 00h TMMR = 81h E1TCR1 = 80h, E1TCR2 = 00h, TCR3 = 00h Transparent Operation on DS26521, DS26524 and DS26528 for T1 ModeRegister Configurations:
RMMR = 80h T1RCR1 = CAh, T1RCR2 = 0Ch TMMR = 80h T1TCR1 = 64h, T1TCR2 = 00h, TCR3 = 00h ConclusionIf you have further questions about transparent operation on Dallas Semiconductor framers or SCTs, contact the Telecommunications Applications Support Team via email at var name = "telecom.support @"; var domain = "dalsemi.com"; document.write ("" + name + domain + ""); telecom. or call 972-371-6555.
or transmitted without host intervention.
The user must take care to not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode, map both controllers to the FDL. HDLC # 1 and HDLC # 2 are identical in operation and therefore, when applicable, each DS21x52 register bit will be mapped to two addresses.
DS21x52 Register: HCR: HDLC Control Register
DS21x52 Register Address: 00 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RBR | BOCC | 37.3 |
| 6 | RHR | HxRC * | 31.7 32.7 |
| 5 | TFS | HxTC * | 90.3 A0.3 |
| 4 | THR | HxTC * | 90.5 A0.5 |
| 3 | TABT | HxTC * | See below |
| 2 | TEOM | HxTC * | 90.2 A0.2 |
| 1 | TZSD | HxTC * | 90.1 A0.1 |
| 0 | TCRCD | HxTC * | 90.0 A0.0 |
HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. HxRC refers to H1RC and H2RC located at addresses 31 Hex and 32 Hex respectively. TABT, bit 3, has been incorporated into the Transmit HDLC Reset (THR) bit. DS21x52 Register: HSR: HDLC Status Register
DS21x52 Register Address: 01 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RBOC | SR8 | 24.0 |
| 6 | RPE | SR6 SR7 | 20.5 22.5 |
| 5 | RPS | SR6 SR7 | 20.4 22.4 |
| 4 | RHALF | SR6 SR7 | 20.3 * 22.3 * |
| 3 | RNE | SR6 SR7 | 20.2 22.2 |
| 2 | THALF | SR6 SR7 | 20.1 * 22.1 * |
| 1 | TNF | SR6 SR7 | 20.0 22.0 |
| 0 | TMEND | SR6 SR7 | 20.6 22.6 |
The status bits for HDLC # 1 have been mapped to Status Register 6 (SR6) in the DS2155. The status bits for HDLC # 2 have been mapped to Status Register 7 (SR7) in the DS2155. THALF, bit 2, has been renamed to TLWM. In the DS21x52, THALF is set when the transmit 64-byte FIFO empties beyond the halfway point. For the DS2155, the TLWM bit will be set when the transmit 128-byte FIFO empties beyond the low water mark as defined by the TFLWM0-TFLWM2 bits located in the FIFO control register (H1FC, H2FC). The low water mark is programmable to one of 8 different levels. RHALF, bit 4, has been renamed to RHWM. In the DS21x52, RHALF is set when the receive 64-byte FIFO fills beyond the halfway point. For the DS2155, the RHWM bit will be set when the receive 128-byte FIFO fills beyond the high water mark as defined by the RFHWM0-RFHWM2 bits located in the FIFO control register (H1FC, H2FC). The high water mark is programmable to one of 8 different levels. DS21x52 Register: HIMR: HDLC Interrupt Mas k Register
DS21x52 Register Address: 02 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RBOC | IMR8 | 25.0 |
| 6 | RPE | IMR6 IMR7 | 21.5 23.5 |
| 5 | RPS | IMR6 IMR7 | 21.4 23.4 |
| 4 | RHALF | IMR6 IMR7 | 21.3 * 23.3 * |
| 3 | RNE | IMR6 IMR7 | 21.2 23.2 |
| 2 | THALF | IMR6 IMR7 | 21.1 * 23.1 * |
| 1 | TNF | IMR6 IMR7 | 21.0 23.0 |
| 0 | TMEND | IMR6 IMR7 | 21.6 23.6 |
The interrupt mask bits for HDLC # 1 have been mapped to HDLC Interrupt Mask Register 6 (IMR6) in the DS2155. The interrupt mask bits for HDLC # 2 have been mapped to HDLC Interrupt Mask Register 7 (IMR7) in the DS2155. THALF, bit 2, has been renamed to TLWM. When THALF is enabled in the DS21x52, the device will generate an interrupt when the transmit 64-byte FIFO empties beyond the halfway point. For the DS2155, the device will generate an interrupt, if TLWM is enabled, when the transmit 128-byte FIFO empties beyond the low water mark as defined by the TFLWM0-TFLWM2 bits located in the FIFO control register (H1FC, H2FC). The low water mark is programmable to one of 8 different levels. RHALF, bit 4, has been renamed to RLWM. When RHALF is enabled in the DS21x52, the device will generate an interrupt when the receive 64-byte FIFO fills beyond the halfway point. For the DS2155, the device will generate an interrupt, if RHWM is enabled, when the receive 128-byte FIFO fills beyond the high w ater mark as defined by the RFHWM0-RFHWM2 bits located in the FIFO control register (H1FC, H2FC). The high water mark is programmable to one of 8 different levels. DS21x52 Register: RHIR: Receive HDLC Information Register
DS21x52 Register Address: 03 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RABT | INFO5 INFO6 | See below |
| 6 | RCRCE | INFO5 INFO6 | See below |
| 5 | ROVR | INFO5 INFO6 | See below |
| 4 | RVM | INFO5 INFO6 | See below |
| 3 | REMPTY | INFO5 INFO6 | 2E.3 2F.3 |
| 2 | POK | INFO5 INFO6 | See below |
| 1 | CBYTE | HxRPBA * | 9C.7 * AC.7 * |
| 0 | OBYTE | INFO4 * | # 1 2D.1 * # 2 2D.3 * |
The HDLC information bits for HDLC # 1 have been mapped to the Receive HDLC # 1 Information Register, INFO5. The HDLC information bits for HDLC # 2 have been mapped to the Receive HDLC # 2 Information Register, INFO6. OBYTE, bit 0, is renamed as H1OBT for HDLC # 1 and H2OBT for HDLC # 2. Both H1OBT & H2OBT can be found in the HDLC Event Information Register (INFO4, address 2D Hex). There is no new functionality associated with this bit. HxRPBA refers to H1RPBA and H2RPBA, located at addresses 9C Hex and AC Hex respectively. CBYTE, bit 1, has been renamed as MS. Unlike the operation of the CBYTE bit in the DS21x52, the MS bit will be low when the byte available for reading the receive FIFO is the last byte of a message. MS will be high when the byte available for reading is the first byte of the continuation of a message. POK, bit 2, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RVM, bit 4, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. ROVR, bit 5, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RCRCE, bit 6, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. RABT, bit 7, has been incorporated into the Receive Packet Status bits (PS0-PS2) located in INFO5 and INFO6. DS21x52 Register: RBOC: Receive Bit Oriented Code Register
DS21x52 Register Address: 04 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | LBD | SR2 | 18.7 |
| 6 | BD | INFO2 | 11.6 |
| 5 | BOC5 | See below | See below |
| 4 | BOC4 | See below | See below |
| 3 | BOC3 | See below | See below |
| 2 | BOC2 | See below | See below |
| 1 | BOC1 | See below | See below |
| 0 | BOC0 | See below | See below |
BOC0-BOC5, bits 0-5, share the RFDL register in the DS2155. See section 22 of the DS2155 for additional information on the BOC controller.DS21x52 Register: RHFR: Receive HDLC FIFO
DS21x52 Register Address: 05 Hex
The Receive HDLC FIFO Register has been relocated to address 9E Hex for HDLC # 1 and AE Hex for HDLC # 2. The lower 7 bits of the Receive Packet Bytes Available registers (H1RPBA, H2RPBA) indicate the number of bytes that can be read from the receive FIFO. The value indicated by the lower seven bits in these registers informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC Information register for detailed message status. See section 24.4 .2 of the DS2155 data sheet for additional information. DS21x52 Register: THIR: Transmit HDLC Information Register
DS21x52 Register Address: 06 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | - | - | - |
| 6 | - | - | - |
| 5 | - | - | - |
| 4 | - | - | - |
| 3 | - | - | - |
| 2 | TEMPTY | INFO5 INFO6 | 2E.5 2F.5 |
| 1 | TFULL | INFO5 INFO6 | 2E.4 2F.4 |
| 0 | TUDR | INFO4 * | # 1 2D.1 * # 2 2D.3 * |
TUDR, bit 0, is renamed as H1UDR for HDLC # 1 and H2UDR for HDLC # 2. Both H1UDR & H2UDR can be found in the HDLC Event Information Register (INFO4, address 2D Hex). There is no new functionality associated with this bit . DS21x52 Register: TBOC: Transmit Bit Oriented Code Register
DS21x52 Register Address: 07 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | SBOC | BOCC | 37.0 |
| 6 | HBEN | HxTC * | 90.4 * A0.4 * |
| 5 | BOC5 | See below | See below |
| 4 | BOC4 | See below | See below |
| 3 | BOC3 | See below | See below |
| 2 | BOC2 | See below | See below |
| 1 | BOC1 | See below | See below |
| 0 | BOC0 | See below | See below |
BOC0-BOC5, bits 0-5, share the TFDL register in the DS2155. See section 22 of the DS2155 for additional information on the BOC controller. HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. HBEN, bit 6, has been renamed as THMS. The THMS bit behaves in a different manner than the HBEN bit. See section 22 and 24 of the DS2155 for more information about the HDLCs operation. DS21x52 Register: THFR: Transmit HDLC FIFO
DS21x52 Register Address: 08 Hex
The Transmit HDLC FIFO Register has been relocated to address 9D Hex for HDLC # 1 and AD Hex for HDLC # 2. The Transmit FIFO Buffer Available registers (H1TFBA, H2TFBA) indicate the number of bytes that can be written into the transmit FIFOs. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer DS21x52 Register: RDC1: Receive HDLC DS0 Control Register 1
DS21x52 Register Address: 90 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RDS0E | HxRC | 31.6 * 32.6 * |
| 6 | - | - | - |
| 5 | RDS0M | See below | See below |
| 4 | RD4 | See below | See below |
| 3 | RD3 | See below | See below |
| 2 | RD2 | See below | See below |
| 1 | RD1 | See below | See below |
| 0 | RD0 | See below | See below |
RD0 through RD4, bits 0 to 4, and RDS0M, bit 5, have been replaced by registers H1RCS1 to H1RCS4 for HDLC # 1 and H2RCS1 to H2RCS4 for HDLC # 2. Any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel (s) any combination of bits within the channel (s) can be avoided. See section 24.3 of the DS2155 for additional information on mapping the HDLC data to channels. HxRC refers to H1RC and H2RC located at addresses 31 Hex and 32 Hex respectively. RDS0E, bit 7, has been renamed to RHMS. The operation of this bit is inverted from that of the DS21x52. See section 24 of the DS2155 for additional information. DS21x52 Register: RDC2: Receive HDLC DS0 Control Register 2
DS21x52 Register Address: 91 Hex
Receive HDLC DS0 Control Register 2 has been relocated to 96 Hex for HDLC # 1 and A6 Hex for HDLC # 2. DS21x52 Register: TDC1: Transmit HDLC DS0 Control Register 1
DS21x52 Register Address: 92 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | TDS0E | HxTC | 90.4 * A0.4 * |
| 6 | - | - | - |
| 5 | TDS0M | See below | See below |
| 4 | TD4 | See below | See below |
| 3 | TD3 | See below | See below |
| 2 | TD2 | See below | See below |
| 1 | TD1 | See below | See below |
| 1 | TD1 | See below | See below |
TD0 through TD4, bits 0 to 4, and TDS0M, bit 5, have been replaced by registers H1TCS1 to H1TCS4 for HDLC # 1 and H2TCS1 to H2TCS4 for HDLC # 2. Any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel (s) any combination of bits within the channel (s) can be avoided. See section 24.3 of the DS2155 for additional information on mapping the HDLC data to channels. HxTC refers to H1TC and H2TC located at addresses 90 Hex and A0 Hex respectively. TDS0E, bit 7, has been renamed to THMS. The operation of this bit is inverted from that of the DS21x52. See section 24 of the DS2155 for additional information. DS21x52 Register: TDC2: Transmit HDLC DS0 Control Register 2
DS21x52 Register Address: 93 Hex
Transmit HDLC DS0 Control Register 2 has been relocated to 9B Hex for HDLC # 1 and AB Hex for HDLC # 2. DS21x52 Register: RFDL: Receive FDL Register
DS21x52 Register Address: 28 Hex
The Receive FDL Register has been relocated to address C0 Hex. The RFDL register will operate as the receive BOC message and information register when the receive BOC function is enabled by setting BOCC.4 to 1. The lower six bits of the RFDL register will contain the BOC message bits when used in this configuration. See section 22 of the DS2155 data sheet for more information. DS21x52 Register: RFDLM1, RFDLM2: Receive FDL Match Registers
DS21x52 Register Address: 29 & 2A Hex
Receive FDL Match Registers 1 and 2 have been relocated to address C2 Hex and C3 Hex, respectively. DS21x52 Register: TFDL: Transmit FDL Register
DS21x52 Register Address: 7E Hex
The Transmit FDL Register has been relocated to address C1 Hex. The TFDL register will operate as the transmit BOC message register when the transmit BOC function is enabled by setting BOCC.0 to 1. The lower six bits of the TFDL register will contain the BOC message to be transmitted. See section 22 of the DS2155 data sheet for additional information. Line Interface, Programmable In-Band Loop Code, and Transmit Transparency Registers DS21x52 Register: LICR: Line Interface Control Register
DS21x52 Register Address: 7C Hex
DS21x52 Register: IBCC: In-Band Code Control Register
DS21x52 Register Address: 12 Hex
DS21x52 Register: TCD: Transmit Code Definition Register
DS21x52 Register Address: 13 Hex
DS21x52 Register: RUPCD: Receive Up Code Definition Register
DS21x52 Register Address: 14 Hex
DS21x52 Register: RDNCD: Receive Down Code Definition Register
DS21x52 Register Address: 15 Hex
DS21x52 Register: TTR1, TTR2, TTR3: Transmit Transparency Registers
DS21x52 Register Address: 39, 3A, 3B Hex
| DS21x52 Register | DS21x52 Register Abbreviation | DS2155 Register Abbreviation | DS2155 Address (Hex) |
| Line Interface Control Register | LICR (7C Hex) | LIC1 | 78 |
| In-Band Code Control Register | IBCC (12 Hex) | IBCC | B6 |
| Transmit Code Definition Register | TCD (13 Hex) | TCD1 * | B7 * |
| Receive Up Code Definition Register | RUPCD (14 Hex) | RUPCD1 * | B9 * |
| Receive Down Code Definition Register | RDNCD (15 Hex) | RDNCD1 * | BB * |
| Transmit Transparency Register 1 | TTR1 | SSIE1 | 08 |
| Transmit Transparency Register 2 | TTR2 | SSIE2 | 09 |
| Transmit Transparency Register 3 | TTR3 | SSIE3 | 0A |
The DS2155's programmable in-band loop code generation and detection includes support for 16-bit codes. In adding this feature a second register has been added for transmit code definition and receive up / down code definition. For generation or detection of 8 bit patterns, both of the appropriate definition registers must be filled with the same value. See section 26 of the DS2155 data sheet for additional information. Interleaved PCM Bus Operation Register The interleave bus operation has been converted to full software control in the DS2155 and the external pins associated with this option have been reassigned to the extended system information bus function. See section 29 for more detail on the interleaved PCM bus operation.
DS21x54 Register: IB Interleaved Bus Operation Register
DS21x54 Register Address: 94 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | - | - | - |
| 6 | - | - | - |
| 5 | - | - | - |
| 4 | - | - | - |
| 3 | IBOEN | IBOC | C5.3 |
| 2 | INTSEL | IBOC | C5.3 * |
| 1 | MSEL0 | See below | See below |
| 0 | MSEL1 | See below | See below |
MSEL0 and MSEL1 are not included in the DS2155. INTSEL, bit 2, has been renamed IBOSEL. There is no new functionality associated with this control bit. 3. Software Considerations: DS2155 vs. DS21x54 (E1) This section will present the registers for the DS21354 and DS21554. The registers are presented in the order that they appear in the DS21354 and DS21554 data sheet.
ID RegisterDS21x54 Register: IDR: Device Identification Register
DS21x54 Register Address: 0F Hex
The Device Identification Register (IDR) for the DS2155 is located at the same address as the IDR for the DS21x54. The upper four bits display the DS2155 ID (1011) and the lower four bits display the die revision. Receive Control Registers DS21x54 Register: RCR1 : Receive Control Register 1
DS21x54 Register Address: 10 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RSMF | IOCR1 | 01.6 * |
| 6 | RSM | IOCR1 | 01.5 * |
| 5 | RSIO | IOCR1 | 01.4 |
| 4 | - | - | - |
| 3 | - | - | - |
| 2 | FRC | E1RCR1 | 33.2 |
| 1 | SYNCE | E1RCR1 | 33.1 |
| 0 | RESYNC | E1RCR1 | 33.0 |
RSM, bit 6, has been renamed as RSMS1. There is no new functionality associated with the bit. RSDW, bit 7, has been renamed as RSMS2. There is no new functionality associated with the bit. DS21x54 Register: RCR2: Receive Control Register 2
DS21x54 Register Address: 11 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | Sa8S | E1RCR2 | 34.7 |
| 6 | Sa7S | E1RCR2 | 34.6 |
| 5 | Sa6S | E1RCR2 | 34.5 |
| 4 | Sa5S | E1RCR2 | 34.4 |
| 3 | Sa4S | E1RCR2 | 34.3 |
| 2 | RBCS | IOCR2 | 02.0 * |
| 1 | RESE | ESCR | 4F.0 |
| 0 | - | - | - |
RBCS, bit 2, has been renamed as RSCLKM. There is no new functionality associated with the bit. Transmit Control Registers DS21x54 Register: TCR1: Transmit Control Register 1
DS21x54 Register Address: 12 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | ODF | IOCR1 | 01.0 |
| 6 | TFPT | E1TCR1 | 35.7 |
| 5 | T16S | E1TCR1 | 35.6 |
| 4 | TUA1 | E1TCR1 | 35.5 |
| 3 | TsiS | E1TCR1 | 35.4 |
| 2 | TSA1 | E1TCR1 | 35.3 |
| 1 | TSM | IOCR1 | 01.2 |
| 0 | TSIO | IOCR1 | 01.1 |
DS21x54 Register: TCR2: Transmit Control Register 2
DS21x54 Register Address: 13 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | Sa8S | E1TCR2 | 36.7 |
| 6 | Sa7S | E1TCR2 | 36.6 |
| 5 | Sa6S | E1TCR2 | 36.5 |
| 4 | Sa5S | E1TCR2 | 36.4 |
| 3 | Sa4S | E1TCR2 | 36.3 |
| 2 | ODM | CCR1 | 70.4 |
| 1 | AEBE | E1TCR2 | 36.2 |
| 0 | PF | CCR1 | 70.0 * |
PF, bit 0, has been renamed as RLOSF. There is no new functionality associated with the bit. Common Control Registers DS21x54 Register: CCR1: Common Control Register 1
DS21x54 Register Address: 14 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | FLB | LBCR | 4A.0 |
| 6 | THDB3 | E1TCR1 | 35.2 |
| 5 | TG802 | E1TCR1 | 35.1 |
| 4 | TCRC4 | E1TCR1 | 35.0 |
| 3 | RSM | E1RCR1 | 33.6 * |
| 2 | RHDB3 | E1RCR1 | 33.5 |
| 1 | RG802 | E1RCR1 | 33.4 |
| 0 | RCRC4 | E1RCR1 | 33.3 |
RSM, bit 3, has been renamed as RSIGM. There is no new functionality associated with the bit. DS21x54 Register: CCR2: Common Control Register 2
DS21x54 Register Address: 1A Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | ECUS | ERCNT | 41.5 |
| 6 | VCRFS | ERCNT | 41.3 |
| 5 | AAIS | E1TCR2 | 36.1 |
| 4 | ARA | E1TCR2 | 36.0 |
| 3 | RSERC | E1RCR1 | 33.7 |
| 2 | LOTCMC | CCR1 | See below |
| 1 | RFF | SIGCR | 40.3 |
| 0 | RFE | SIGCR | 40.4 |
LOTCMC, bit 2, has been combined with other functions to simplify the selection of the transmit clock source. The two bits, Transmit Clock Source Select 0 (TCSS0) and Transmit Clock Source Select 1 (TCSS1), are located in the DS2155's Common Control Register 1 (CCR1, address 70 Hex) in bit positions 1 and 2 respectively. DS21x54 Register: CCR3: Common Control Register 3
DS21x54 Register Address: 1B Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | TESE | ESCR | 4F.4 |
| 6 | TCBFS | See Below | See Below |
| 5 | TIRFS | See Below | See Below |
| 4 | - | - | - |
| 3 | RSRE | PCPR | 28.6 * |
| 2 | THSE | PCPR | 28.3 * |
| 1 | TBCS | IOCR2 | 02.1 * |
| 0 | RCLA | E1RCR2 | 34.0 |
TBCS, bit 1, has been renamed as TSCLKM. There is no new functionality associated with this bit. THSE, bit 2, has been renamed as THSCS. See sections 7 and 17 of the DS2155 data sheet for information on per-channel register operation . RSRE, bit 3, has been renamed as RSRCS. See sections 7 and 17 of the DS2155 data sheet for additional information on receive signaling re-insertion. Control bit 5, TIRFS, has been incorporated in the new functionality for idle code generation. See section 18 of the DS2155 data sheet for more detail. Control bit 6, TCBFS, has been incorporated into the per-channel register operation. See sections 7 and 17 of the DS2155 data sheet for additional information. DS21x54 Register: CCR4: Common Control Register 4
DS21x54 Register Address: A8 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RLB | LBCR | 4A.2 |
| 6 | LLB | LBCR | 4A.3 |
| 5 | LIAIS | LIC2 | 79.4 * |
| 4 | TCM4 | TDS0SEL | 74.4 |
| 3 | TCM3 | TDS0SEL | 74.3 |
| 2 | TCM2 | TDS0SEL | 74.2 |
| 1 | TCM1 | TDS0SEL | 74.1 |
| 0 | TCM0 | TDS0SEL | 74.0 |
LIAIS, bit 1, has been renamed as TUA1. There is no new functionality associated with this bit. DS21x54 Register: CCR5: Common Control Register 5
DS21x54 Register Address: AA Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | LIRST | LIC2 | 79.6 |
| 6 | RESA | ESCR | 4F.3 * |
| 5 | TESA | ESCR | 4F.7 * |
| 4 | RCM4 | RDS0SEL | 76.4 |
| 3 | RCM3 | RDS0SEL | 76.3 |
| 2 | RCM2 | RDS0SEL | 76.2 |
| 1 | RCM1 | RDS0SEL | 76.1 |
| 0 | RCM0 | RDS0SEL | 76.0 |
TESA, bit 5, has been renamed as TESALGN. There is no new functionality associated with the bit. RESA, bit 6, has been renamed as RESALGN. There is no new functionality associated with the bit. DS21x54 Register: CCR6: Common Control Register 6
DS21x54 Register Address: 1D Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | LIUODO | LIC2 | 79.0 * |
| 6 | CDIG | LIC3 | 7A.0 * |
| 5 | LIUSI | LIC3 | 7A.2 * |
| 4 | - | - | - |
| 3 | - | - | - |
| 2 | TCLKSRC | CCR1 | See below |
| 1 | RESR | ESCR | 4F.2 |
| 0 | TESR | ESCR | 4F.6 |
DS21x54 Register Address: 08 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | TESF | SR5 | 1E.5 |
| 6 | TESE | SR5 | 1E.4 * |
| 5 | JALT | SR1 | 16.4 |
| 4 | RESF | SR5 | 1E.2 |
| 3 | RESE | SR5 | 1E.1 * |
| 2 | CRCRC | INFO3 | 12.2 |
| 1 | FASRC | INFO3 | 12.1 |
| 0 | CASRC | INFO3 | 12.0 |
RESE, bit 3, has been renamed as RESEM. There is no new functionality associated with this bit. TESE, bit 6, has been renamed as TESEM. There is no new functionality associated with this bit. DS21x54 Register: SSR: Synchronizer Status Register
DS21x54 Register Address: 1E Hex
The Synchronizer Status Register has been relocated to address 30 Hex in the DS2155. DS21x54 Register: SR1: Status Register 1
DS21x54 Register Address: 06 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RSA1 | SR4 | 1C.6 |
| 6 | RDMA | SR3 | 1A.1 |
| 5 | RSA0 | SR4 | 1C.5 |
| 4 | RSLIP | SR5 | 1E.0 |
| 3 | RUA1 | SR2 | 18.2 |
| 2 | RRA | SR3 | 1A.0 |
| 1 | RCL | SR1 | 16.3 * |
| 0 | RLOS | SR2 | 18.0 |
RCL, bit 1, has been renamed as LRCL. No additional functionality is associated with this bit. DS21x54 Register: SR2: Status Register 2
DS21x54 Register Address: 07 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RMF | SR4 | 1C.2 |
| 6 | RAF | SR4 | 1C.0 |
| 5 | TMF | SR4 | 1C.4 |
| 4 | SEC | SR1 | 16.6 * |
| 3 | TAF | SR4 | 1C.3 |
| 2 | LOTC | SR3 | 1A.4 |
| 1 | RCMF | SR4 | 1C.1 |
| 0 | TSLIP | SR5 | 1E.3 |
SEC, bit 5, has been renamed as TIMER. In the DS21x54, this bit was set on increments of one second (referenced to RCLK). In the DS2155, this bit follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). In T1 mode, this bit can be configured to set on increments of 1 second or 42ms (referenced to RCLK). DS21x54 Register: IMR1: Interrupt Mask Register 1
DS21x54 Register Address: 16 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RSA1 | IMR4 | 1D.6 |
| 6 | RDMA | IMR3 | 1B.1 |
| 5 | RSA0 | IMR4 | 1D.5 |
| 4 | RSLIP | IMR5 | 1F.0 |
| 3 | RUA1 | IMR2 | 19.2 |
| 2 | RRA | IMR3 | 1B.0 |
| 1 | RCL | IMR1 | 17.3 * |
| 0 | RLOS | IMR2 | 19.0 |
RCL, bit 1, has been renamed as LRCL. No additional functionality is associated with this bit. DS21x54 Register: IMR2: Interrupt Mask Register 2
DS21x54 Register Address: 17 Hex
| Bit # | Name | 55 Abbrv. | 55 Addr.Bit |
| 7 | RMF | IMR4 | 1D.2 |
| 6 | RAF | IMR4 | 1D.0 |
| 5 | TMF | IMR4 | 1D.4 |
| 4 | SEC | IMR1 | 17.6 * |
| 3 | TAF | IMR4 | 1D.3 |
| 2 | LOTC | IMR3 | 1B.4 |
| 1 | RCMF | IMR4 | 1D.1 |
| 0 | TSLIP | IMR5 | 1F.3 |
SEC, bit 5, has been renamed as TIMER. In the DS21x54, this bit enabled the interrupt on increments of one second (referenced to RCLK). In the DS2155, this bit follows the error counter update interval as determined by the ECUS bit in the Error Counter Configuration Register (ERCNT). In T1 mode, this bit can be configured to interrupt on increments of 1 second or 42ms (referenced to RCLK). Error Count RegistersThe error count registers have been kept intact, but have been relocated. In addition, all of the count registers are now 16-bit registers because the registers that were shared in the DS21x54 are no longer shared in the DS2155. See section 15 in the DS2155 data sheet for additional information on the error count registers.
DS21x54 Registers: VCR1, VCR2: Bipolar Violation Count Register 1 & 2
DS21x54 Register Address: 00, 01 Hex
DS21x54 Registers: CRCCR1, CRCCR2: CRC4 Count Register 1 & 2
DS21x54 Register Address: 02 Hex (Same as FASCR1), 03 Hex
DS21x54 Register: FASCR1, FASCR2: FAS Error Count Register 1 & 2
DS21x54 Register Address: 02 Hex (Same as CRCCR1), 04 Hex (Same as EBCR1)
DS21x54 Register: EBCR1, EBCR2: E-Bit Count Register 1 & 2
DS21x54 Register Address: 04 Hex (Same as FASCR2), 05 Hex
| DS21x54 Register | DS21x54 Register Abbreviation | DS2155 Register Abbreviation | DS2155 Address (Hex) |
| Bipolar Violation Count Register 1 | VCR1 (00 Hex) | LCVCR1 | 42 |
| Bipolar Violation Count Register 2 | VCR2 (01 Hex) | LCVCR2 | 43 |
| CRC4 Count Register 1 | CRCCR1 (02 Hex) * | PCVCR1 | 44 |
| CRC4 Count Register 2 | CRCCR2 (03 Hex) | PCVCR2 | 45 |
| FAS Error Count Register 1 | FASCR1 (02 Hex) * | FOSCR1 | 46 |
| FAS Error Count Register 2 | FASCR2 (04 Hex) * | FOSCR2 | 47 |
| E-Bit Error Count Register 1 | EBCR1 (04 Hex) * | EBCR2 | 48 |
| E-Bit Error Count Register 2 | EBCR2 (05 Hex) | EBCR2 | 49 |
In the DS21x54, CRCCR1 and FASCR1 shared the count register located at address 02 Hex. The two error counters no longer share a register in the DS2155. Additionally, FASCR2 and EBCR1 shared the count register located at address 04 Hex. These two error counters no longer share a register in the DS2155. DS0 Monitoring Function Registers Both the Transmit DS0 Monitor Register and Receive DS0 Monitor Register has been relocated to a new address.
DS21x54 Register: TDS0M: Transmit DS0 Monitor Register
DS21x54 Register Address: A9 Hex
DS21x54 Register: RDS0M: Receive DS0 Monitor Register
DS21x54 Register Address: AB Hex
| DS21x54 Register | DS21x54 Register Abbreviation | DS2155 Register Abbreviation | DS2155 Address (Hex) |
| Transmit DS0 Monitor Register | TDS0M (A9 Hex) | TDS0M | 75 |
| Receive DS0 Monitor Register | RDS0M (AB Hex) | RDS0M | 77 |
Signaling RegistersThe Transmit Signaling Registers and Receive Signaling Registers have been relocated to 50-5F Hex and 60-6F Hex, respectively. Additionally, the signaling information contained in the signaling registers has been rearranged. See section 17 of the DS2155 data sheet for additional information on signaling operation.
DS21x54 Register: RS1 to RS16: Receive Signaling Registers
DS21x54 Register Address: 30 to 3F Hex
The Receive signaling registers have been relocated to 60-6F Hex The following table shows the new the arrangement for the Receive Signaling Registers. Transmit Signaling Registers (T1 Mode, ESF Format)
| Register Name | DS2155 Address | ||||||||
| (MSB) | (LSB) | ||||||||
| RS1 | 60 | CH2-A | CH2-B | CH2-C | CH2-D | CH1-A | CH1-B | CH1-C | CH1-D |
| RS2 | 61 | CH4-A | CH4-B | CH4-C | CH4-D | CH3-A | CH3-B | CH3-C | CH3-D |
| RS3 | 62 | CH6-A | CH6-B | CH6-C | CH6-D | CH5-A | CH5-B | CH5-C | CH5-D |
| RS4 | 63 | CH8-A | CH8-B | CH8-C | CH8-D | CH7-A | CH7-B | CH7-C | CH7-D |
| RS5 | 64 | CH10-A | CH10-B | CH10-C | CH10-D | CH9-A | CH9-B | CH9-C | CH9-D |
| RS6 | 65 | CH12-A | CH12-B | CH12-C | CH12-D | CH11-A | CH11-B | CH11-C | CH11-D |
| RS7 | 66 | CH14-A | CH14-B | CH14-C | CH14-D | CH13-A | CH13-B | CH13-C | CH13-D |
| RS8 | 67 | CH16-A | CH16-B | CH16-C | CH16-D | CH15-A | CH15-B | CH15-C | CH15-D |
| RS9 | 68 | CH18-A | CH18-B | CH18-C | CH18-D | CH17-A | CH17-B | CH17-C | CH17-D |
| RS10 | 69 | CH20-A | CH20-B | CH20-C | CH20-D | CH19-A | CH19-B | CH19-C | CH19-D |
| RS11 | 6A | CH22-A | CH22-B | CH22-C | CH22-D | CH21-A | CH21-B | CH21-C | CH21-D |
| RS12 | 6B | CH24-A | CH24-B | CH24-C | CH24-D | CH23-A | CH23-B | CH23-C | CH23-D |
| RS13 | 6C | CH26-A | CH26-B | CH26-C | CH26-D | CH25-A | CH25-B | CH25-C | CH25-D |
| RS14 | 6D | CH28-A | CH28-B | CH28-C | CH28-D | CH27-A | CH27-B | CH27-C | CH27-D |
| RS15 | 6E | CH30-A | CH30-B | CH30-C | CH30-D | CH29-A | CH29-B | CH29-C | CH29-D |
| RS16 | 6F | CH32-A | CH32-B | CH32-C | CH32-D | CH31-A | CH31-B | CH31-C | CH31-D |
DS21x54 Register: TS1 to TS16: Transmit Signaling Registers
DS21x54 Register Address: 40 to 4F Hex
Transmit Signaling Registers 1 through 16 can be found at addresses 50 Hex through 5F Hex. In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "Channel" numbering, TS0 through TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are labeled channel 15 through channel 30. See table 17-1 in the DS2155 for more information. The following tables show the new the arrangement for the Transmit Signaling Registers for CAS and CCS formats. Transmit Signaling Registers (E1 Mode, CAS Format)
| Register Name | DS2155 Address | ||||||||
| (MSB) | (LSB) | ||||||||
| TS1 | 50 | 0 | 0 | 0 | 0 | X | Y | X | X |
| TS2 | 51 | CH2-A | CH2-B | CH2-C | CH2-D | CH1-A | CH1-B | CH1-C | CH1-D |
| TS3 | 52 | CH4-A | CH4-B | CH4-C | CH4-D | CH3-A | CH3-B | CH3-C | CH3-D |
| TS4 | 53 | CH6-A | CH6-B | CH6-C | CH6-D | CH5-A | CH5-B | CH5-C | CH5-D |
| TS5 | 54 | CH8-A | CH8-B | CH8-C | CH8-D | CH7-A | CH7-B | CH7-C | CH7-D |
| TS6 | 55 | CH10-A | CH10-B | CH10-C | CH10-D | CH9-A | CH9-B | CH9-C | CH9-D |
| TS7 | 56 | CH12-A | CH12-B | CH12-C | CH12-D | CH11-A | CH11-B | CH11-C | CH11-D |
| TS8 | 57 | CH14-A | CH14-B | CH14-C | CH14-D | CH13-A | CH13-B | CH13-C | CH13-D |
| TS9 | 58 | CH16-A | CH16-B | CH16-C | CH16-D | CH15-A | CH15-B | CH15-C | CH15-D |
| TS10 | 59 | CH18-A | CH18-B | CH18-C | CH18-D | CH17-A | CH17-B | CH17-C | CH17-D |
| TS11 | 5A | CH20-A | CH20-B | CH20-C | CH20-D | CH19-A | CH19-B | CH19-C | CH19-D |
| TS12 | 5B | CH22-A | CH22-B | CH22-C | CH22-D | CH21-A | CH21-B | CH21-C | CH21-D |
| TS13 | 5C | CH24-A | CH24-B | CH24-C | CH24-D | CH23-A | CH23-B | CH23-C | CH23-D |
| TS14 | 5D | CH26-A | CH26-B | CH26-C | CH26-D | CH25-A | CH25-B | CH25-C | CH25-D |
| TS15 | 5E | CH28-A | CH28-B | CH28-C | CH28-D | CH27-A | CH27-B | CH27-C | CH27-D |
| TS16 | 5F | CH30-A | CH30-B | CH30-C | CH30-D | CH29-A | CH29-B | CH29-C | CH29-D |
Transmit Signaling Registers (E1 Mode, CCS Format)
| Register Name | DS2155 Address | ||||||||
| (MSB) | (LSB) | ||||||||
| TS1 | 50 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| TS2 | 51 | 17 | 18 | 19 | 20 | 9 | 10 | 11 | 12 |
| TS3 | 52 | 33 | 34 | 35 | 36 | 25 | 26 | 27 | 28 |
| TS4 | 53 | 49 | 50 | 51 | 52 | 41 | 42 | 43 | 44 |
| TS5 | 54 | 65 | 66 | 67 | 68 | 57 | 58 | 59 | 60 |
| TS6 | 55 | 81 | 82 | 83 | 84 | 73 | 74 | 75 | 76 |
| TS7 | 56 | 97 | 98 | 99 | 100 | 89 | 90 | 91 | 92 |
| TS8 | 57 | 113 | 114 | 115 | 116 | 105 | 106 | 107 | 108 |
| TS9 | 58 | 13 | 14 | 15 | 16 | 121 | 122 | 123 | 124 |
| TS10 | 59 | 29 | 30 | 31 | 32 | twenty one | twenty two | twenty three | twenty four |
| TS11 | 5A | 45 | 46 | 47 | 48 | 37 | 38 | 39 | 40 |
| TS12 | 5B | 61 | 62 | 63 | 64 | 53 | 54 | 55 | 56 |
| TS13 | 5C | 77 | 78 | 89 | 80 | 69 | 70 | 71 | 72 |
| TS14 | 5D | 93 | 94 | 95 | 96 | 85 | 86 | 87 | 88 |
| TS15 | 5E | 109 | 110 | 111 | 112 | 101 | 102 | 103 | 104 |
| TS16 | 5F | 125 | 126 | 127 | 128 | 117 | 118 | 119 | 120 |
Per-Channel Code Generation RegistersThe method for generating idle codes has changed in the DS2155. The DS2155 contains a 64-byte Idle Code Array accessed by t
| About Copper Accessories |
Copper Accessories includes Plastic Spool, insulating paint and cable wire, plastic has colorful choose for you .insulating paint has two kinds of packages (200 kg and 1000 kg). cable wire is very flexible .House wiring cables and feeder cables.
Copper Accessories
Copper Accessories,Low Oxygen Copper Rod,Upcast Process Copper Rod,Copper Round Bar
HENAN HUAYANG ELECTRICAL TECHNOLOGY GROUP CO.,LTD , https://www.huaonwire.com